UTBB SOI MOSFETs with gate-source/drain underlap and ground plane (GP) structures for analog/RF applications

In this work, we report on the influence of underlap architecture (L_UL) and ground plane (GP) on the analog/RF performance metrics of Ultra-Thin Body and Buried Oxide (UTBB) Fully-Depleted (FD) SOI MOSFETs with 25 nm gate length. Small-signal transconductance (g_m), gate-to-gate capacitance (C_gg) and the cut-off frequency (f_t) are the figures-of-merit (FoM) of interest. It is shown that longer underlap i.e. L_UL = 10 nm showed lower g_m. However, it is noted that C_gg also decreases as the underlap increases. Thus, the need for trade-off between g_m and C_gg is needed to achieve optimum values of f_t. From this work, it is found that the impact of g_m on f_t is more prominent than C_gg. From another point of view, the impact of different GP structures on g_m and f_t becomes more apparent at longer underlap.