FPGA implementation of DSP applications using HUB floating point technique

In the recent times we see that the digital signal processing applications are increasingly becoming complex which leads to the extensive using of the floating point numbers in the hardware processing implementations. In this paper, we will focus on the various advantages the HUB technique has when implemented on FPGA applications. The one advantage which the HUB floating point technique has that it helps in eliminating the rounding logic on the arithmetic units. In this we have discussed using the adders and the multipliers. The experimental procedure shows that the HUB technique and the corresponding arithmetic unit have the same accuracy level when compared with the standard format. Whereas, after the implementation is being done it reveals that the HUB technique is better as it has improved speed, area and power consumption. However, for some particular sizes HUB multipliers require lot more resources than the one used in standard format.