On the implementation of PFSCL adders

In this paper, implementation of full adders in positive feedback source-coupled logic style (PFSCL) is proposed. Three new architectures for PFSCL full adders are put forward. The first architecture is implemented by using conventional NOR based method. The second architecture is based on the use of configurable cell while the last architecture optimizes the structure by using both the conventional NOR and configurable cell based approaches. The functionality of the proposed architectures is verified through simulations by using TSMC 180 nm CMOS technology parameter on Tanner EDA. Their performance is compared in terms of transistor count, gate count, power, delay and power-delay product. It is found that the Arch-3 presents the best PFSCL full adder design by incorporating the advantageous features of the other two proposed architectures.