一种用于全频带IR-UWB收发器的0.05pJ/p-mV 5阶导数脉冲发生器，采用0.18µm CMOS

2011 IEEE Radio and Wireless Symposium Pub Date : 2011-03-07 DOI:10.1109/RWS.2011.5725432

Xin Wang, S. Fan, B. Qin, Lin Lin, Q. Fang, H Zhao, He Tang, Jianlin Liu, Zitao Shi, Albert Wang, Liwu Yang, Yuhua Cheng

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引用次数: 2

摘要

本文设计了一种全数字全集成五阶高斯脉冲发生器(PG)，用于全频段(3.1GHz-10.6GHz)脉冲无线电超宽带(IR-UWB)收发器SoC。该设计是在0.18µm的CMOS工艺中实现的。采用新型FCC有效各向同性辐射功率(EIRP)感知设计技术对PG进行优化，在100MHz脉冲重复频率(PRF)下，脉冲峰值幅值为533mV，脉宽为418pS。集成5kV ESD保护。这第5高斯PG消耗的最低报告功率为0.05pJ/p-mV，支持数据速率为2.4Gbps。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 0.05pJ/p-mV 5th-derivative pulse generator for full-band IR-UWB transceiver in 0.18µm CMOS

This paper presents design of an all-digital fully-integrated 5th-order Gaussian pulse generator (PG) for full band (3.1GHz–10.6GHz) impulse radio ultra wideband (IR-UWB) transceiver SoC. The design is implemented in a foundry 0.18µm CMOS process. New FCC effective isotropic radiated power (EIRP) aware design technique is used to optimize the PG. Measurement shows peak pulse amplitude of 533mV at 100MHz pulse repeating frequency (PRF) and pulse width of 418pS. 5kV ESD protection is integrated. This 5th Gaussian PG consumes the lowest reported power of 0.05pJ/p-mV and support data rate to 2.4Gbps.

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2011 IEEE Radio and Wireless Symposium

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