模块化DFR:提高设计灵活性的数字延迟反馈储层模型

IF 2.8 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE ACM Transactions on Embedded Computing Systems Pub Date : 2023-09-09 DOI:10.1145/3609105
Sosei Ikeda, Hiromitsu Awano, Takashi Sato
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引用次数: 0

摘要

延迟反馈储层(DFR)是一种结构简单、适合硬件实现的储层计算系统。大多数现有的DFR实现使用模拟电路,需要数模和模数转换器进行接口。然而,数字dfr模拟的是数字域的非线性模拟元件,导致设计灵活性不足,功耗较高。在本文中,我们提出了一种新的模块化DFR模型,适用于全数字化实现。该模型减少了超参数的数量,并允许灵活地选择非线性函数,从而在降低功耗的同时提高了精度。我们进一步提出了两种具有不同非线性函数的DFR实现,在保持相同或更好的精度的同时,实现了10倍的功耗降低和5.3倍的吞吐量提高。
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Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility
A delayed feedback reservoir (DFR) is a type of reservoir computing system well-suited for hardware implementations owing to its simple structure. Most existing DFR implementations use analog circuits that require both digital-to-analog and analog-to-digital converters for interfacing. However, digital DFRs emulate analog nonlinear components in the digital domain, resulting in a lack of design flexibility and higher power consumption. In this paper, we propose a novel modular DFR model that is suitable for fully digital implementations. The proposed model reduces the number of hyperparameters and allows flexibility in the selection of the nonlinear function, which improves the accuracy while reducing the power consumption. We further present two DFR realizations with different nonlinear functions, achieving 10× power reduction and 5.3× throughput improvement while maintaining equal or better accuracy.
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来源期刊
ACM Transactions on Embedded Computing Systems
ACM Transactions on Embedded Computing Systems 工程技术-计算机:软件工程
CiteScore
3.70
自引率
0.00%
发文量
138
审稿时长
6 months
期刊介绍: The design of embedded computing systems, both the software and hardware, increasingly relies on sophisticated algorithms, analytical models, and methodologies. ACM Transactions on Embedded Computing Systems (TECS) aims to present the leading work relating to the analysis, design, behavior, and experience with embedded computing systems.
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