Experimental and Numerical Investigation of Delamination Between Epoxy Molding Compound (EMC) and Metal in Encapsulated Microelectronic Packages

Microelectronics packages play a vital role in not only interconnecting the electronic signals from the die to the printed circuit board (PCB), but also in protecting the chips during the manufacturing process and their subsequent service lives. Epoxy molding compound (EMC) is widely used in electronic packaging due to its superior processing capability and low circuit signal delay. However, interfacial delamination is a common problem in encapsulated silicon devices, particularly at the interface between the copper leadframe (LF) pads and the EMC due to the weaker adhesion strength. Accordingly, the present study employs a double cantilever beam (DCB) experimental testing method and a numerical model based on the virtual crack closure technique (VCCT) to investigate the fracture behavior at the EMC/Cu LF interface in a quad flat no leads (QFN) package. The experiments are performed on an MTS-Acumen microforce tester equipped with a load unit capable of applying a force of 0.01 to 1250 N with a displacement resolution of 0.1 μm. The DCB specimens are prepared with a pre-crack length of 12 mm. The validity of the simulation model is confirmed by comparing the predicted values of the critical strain energy release rate (SERR, G_c) between the EMC and the copper LF pads with the experimental observations. In general, the results show that the G_c value provides a useful parameter for evaluating the delamination risk of encapsulated microelectronics packages and assessing the reliability of alternative package architectures.