利用串扰计算的嵌入式内存逻辑新方法

IF 2.1 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-12-09 DOI:https://dl.acm.org/doi/10.1145/3569917
Prerana Samant, Naveen Kumar Macha, Mostafizur Rahman
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引用次数: 0

摘要

计算的基本元素之一是存储元素。触发器构成了片上系统(SoC)的一个组成部分,并消耗了芯片上的大部分面积。为了满足人工智能、云计算和机器学习等数据密集型应用对高速性能的需求,我们提出将内存与逻辑集成在一起,得到基于串扰计算逻辑运行的内置内存逻辑电路。这些电路被称为串扰内置存储器逻辑(CBML)电路,它利用有害的互连串扰,并巧妙地将这种有害的影响转化为具有嵌入式存储器的计算原理。利用我们新颖的CBML电路技术,计算逻辑,并将结果内在地存储在这些复杂的电路中。无论输入的变化如何,存储的值将被保留,直到下一个逻辑计算周期。这种在逻辑中嵌入存储器的新方法,减少了晶体管数量,提供了高速运算。在本文中,我们利用HSPICE中的16纳米(nm) PTM模型展示了复杂CBML电路的内置存储器特性。基准测试是通过与等效的静态CMOS电路进行比较,以比较晶体管的数量、功率和性能。可以观察到,CBML 4位全加法器(算术电路中普遍存在的关键元件,例如ALU,计数器)消耗的晶体管数量最多减少46%,性能比等效CMOS电路提高27%。该电路是大规模CBML电路的一个示例。此外,其他电路(如3输入AND和CARRY逻辑)的性能提高了60%,晶体管数量减少了40%。CBML电路有可能为特殊设计结构的特殊高速宏铺平道路。
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A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing

One of the essential elements of computing is the memory element. Flip-flops form an integral part of a System-on-Chip (SoC) and consume most of the area on the die. To meet the high-speed performance demands by the data-intensive applications such as artificial intelligence, cloud computing, and machine learning, we propose to integrate memory with the logic to get built-in memory Logic circuits that operate based on the crosstalk computing logic. These circuits are called Crosstalk Built-in Memory Logic (CBML) circuits, which exploit the detrimental interconnect crosstalk and astutely turn this unwanted effect into a computing principle with embedded memory. By virtue of our novel CBML circuit technique, the logic is computed, and the result is stored intrinsically within these complex circuits. The stored values will be retained irrespective of the change in input until the next logic evaluation cycle. This neoteric embedding of memory in logic provides high-speed operation with a reduced number of transistors. In this article, we have manifested the built-in memory feature of the complex CBML circuits using 16 nanometer (nm) PTM models in HSPICE. Benchmarking is performed by comparing with the equivalent static CMOS circuits to compare the number of transistors, power, and performance. It is observed that the number of transistors consumed by CBML 4-bit Full-Adder (the key element prevalent in Arithmetic circuits, e.g., ALU, Counters) is up to 46% less, and performance is improved by 27% over the equivalent CMOS circuits. This circuit serves as an example of a large-scale CBML circuit. Also, the performance improvement achieved by other circuits such as 3-input AND and the CARRY logic is up to 60% along with a 40% reduction in the number of transistors. CBML circuits have the potential to pave the way for special high-speed macros with specifically engineered structures.

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来源期刊
ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems 工程技术-工程:电子与电气
CiteScore
4.80
自引率
4.50%
发文量
86
审稿时长
3 months
期刊介绍: The Journal of Emerging Technologies in Computing Systems invites submissions of original technical papers describing research and development in emerging technologies in computing systems. Major economic and technical challenges are expected to impede the continued scaling of semiconductor devices. This has resulted in the search for alternate mechanical, biological/biochemical, nanoscale electronic, asynchronous and quantum computing and sensor technologies. As the underlying nanotechnologies continue to evolve in the labs of chemists, physicists, and biologists, it has become imperative for computer scientists and engineers to translate the potential of the basic building blocks (analogous to the transistor) emerging from these labs into information systems. Their design will face multiple challenges ranging from the inherent (un)reliability due to the self-assembly nature of the fabrication processes for nanotechnologies, from the complexity due to the sheer volume of nanodevices that will have to be integrated for complex functionality, and from the need to integrate these new nanotechnologies with silicon devices in the same system. The journal provides comprehensive coverage of innovative work in the specification, design analysis, simulation, verification, testing, and evaluation of computing systems constructed out of emerging technologies and advanced semiconductors
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