基于Espresso流密码的伽罗瓦和斐波那契组态的设计空间探索

IF 3.1 4区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE ACM Transactions on Reconfigurable Technology and Systems Pub Date : 2023-06-20 DOI:https://dl.acm.org/doi/10.1145/3567428
Zhengyuan Shi, Cheng Chen, Gangqiang Yang, Hailiang Xiong, Fudong Li, Honggang Hu, Zhiguo Wan
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引用次数: 0

摘要

斐波那契和伽罗瓦是流密码中的两种不同的结构。虽然已经提出了两种配置之间的许多转换,但没有对其FPGA性能进行充分的分析。Espresso流密码为探索这类问题提供了一个理想的样本。128位的秘钥Espresso是以伽罗瓦配置设计的,并且有一个fibonacci配置的Espresso变体被证明具有相同的安全级别。为了充分利用两种配置的效率,我们分别探索了针对面积和吞吐量的硬件优化方法。简而言之,fpga实现的斐波那契密码更适合于资源极度受限或高吞吐量的应用,而伽罗瓦密码在面积和速度上都有所妥协。据我们所知,这是第一个在相对公平的加密安全性下系统比较密码配置的FPGA性能的工作。希望本文的工作能够为加密硬件架构的研究提供参考。
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Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher

Fibonacci and Galois are two different kinds of configurations in stream ciphers. Although many transformations between two configurations have been proposed, there is no sufficient analysis of their FPGA performance. Espresso stream cipher provides an ideal sample to explore such a problem. The 128-bit secret key Espresso is designed in Galois configuration, and there is a Fibonacci-configured Espresso variant proved with the equivalent security level. To fully leverage the efficiency of two configurations, we explore the hardware optimization approaches toward area and throughput, respectively. In short, the FPGA-implemented Fibonacci cipher is more suitable for extremely resource-constrained or high-throughput applications, while the Galois cipher compromises both area and speed. To the best of our knowledge, this is the first work to systematically compare the FPGA performance of cipher configurations under relatively fair cryptographic security. We hope this work can serve as a reference for the cryptography hardware architecture research community.

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来源期刊
ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.90
自引率
8.70%
发文量
79
审稿时长
>12 weeks
期刊介绍: TRETS is the top journal focusing on research in, on, and with reconfigurable systems and on their underlying technology. The scope, rationale, and coverage by other journals are often limited to particular aspects of reconfigurable technology or reconfigurable systems. TRETS is a journal that covers reconfigurability in its own right. Topics that would be appropriate for TRETS would include all levels of reconfigurable system abstractions and all aspects of reconfigurable technology including platforms, programming environments and application successes that support these systems for computing or other applications. -The board and systems architectures of a reconfigurable platform. -Programming environments of reconfigurable systems, especially those designed for use with reconfigurable systems that will lead to increased programmer productivity. -Languages and compilers for reconfigurable systems. -Logic synthesis and related tools, as they relate to reconfigurable systems. -Applications on which success can be demonstrated. The underlying technology from which reconfigurable systems are developed. (Currently this technology is that of FPGAs, but research on the nature and use of follow-on technologies is appropriate for TRETS.) In considering whether a paper is suitable for TRETS, the foremost question should be whether reconfigurability has been essential to success. Topics such as architecture, programming languages, compilers, and environments, logic synthesis, and high performance applications are all suitable if the context is appropriate. For example, an architecture for an embedded application that happens to use FPGAs is not necessarily suitable for TRETS, but an architecture using FPGAs for which the reconfigurability of the FPGAs is an inherent part of the specifications (perhaps due to a need for re-use on multiple applications) would be appropriate for TRETS.
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