多级并行的 DNA 直接编码技术

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-01-17 DOI:10.1109/LCA.2024.3355109
Caden Corontzos;Eitan Frachtenberg
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引用次数: 0

摘要

自 2000 年代初以来,全基因组测序的成本和时间一直在稳步快速下降,导致基因组数据激增。相比之下,数字存储设备容量、CPU 时钟速度和网络带宽的增长率则要温和得多。这种差距意味着,存储、传输和处理基因组测序数据的需求正在超过基础技术的能力。使问题更加复杂的是,用于自然语言或图像的传统数据压缩技术并不适合基因组数据。为了应对这一挑战,人们开发了许多数据压缩技术,在压缩率、计算时间、内存要求和复杂性之间进行了一系列权衡。本文将重点讨论这种权衡的一个极端的具体技术,即双位编码,其中基因组序列中的每个碱基都从其原始的 8 位 ASCII 表示压缩为唯一的双位二进制表示。即使是这种简单的直接编码方案,目前的实现方法也还有很大的改进空间。在这里,我们展示了这种编码可以利用现代计算机体系结构中的多级并行性,最大限度地提高编码和解码效率。我们的开源实现达到了每秒数十亿碱基的编码和解码率,远远高于之前报告的结果。事实上,我们测得的吞吐量通常只受到底层存储介质速度的限制。
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Direct-Coding DNA With Multilevel Parallelism
The cost and time to sequence entire genomes have been on a steady and rapid decline since the early 2000s, leading to an explosion of genomic data. In contrast, the growth rates for digital storage device capacity, CPU clock speed, and networking bandwidth have been much more moderate. This gap means that the need for storing, transmitting, and processing sequenced genomic data is outpacing the capacities of the underlying technologies. Compounding the problem is the fact that traditional data compression techniques used for natural language or images are not optimal for genomic data. To address this challenge, many data-compression techniques have been developed, offering a range of tradeoffs between compression ratio, computation time, memory requirements, and complexity. This paper focuses on a specific technique on one extreme of this tradeoff, namely two-bit coding, wherein every base in a genomic sequence is compressed from its original 8-bit ASCII representation to a unique two-bit binary representation. Even for this simple direct-coding scheme, current implementations leave room for significant performance improvements. Here, we show that this encoding can exploit multiple levels of parallelism in modern computer architectures to maximize encoding and decoding efficiency. Our open-source implementation achieves encoding and decoding rates of billions of bases per second, which are much higher than previously reported results. In fact, our measured throughput is typically limited only by the speed of the underlying storage media.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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