Auto-Labeling for Pattern Recognition of Wafer Defect Maps in Semiconductor Manufacturing

Semiconductor manufacturing technology has been developing rapidly in the last decade, and the advanced process control methodology has also made considerable progress due to the birth of machine learning and deep learning. In practical semiconductor processes, the defect analysis for wafer map is a critical step for improving product quality and yield. These defect patterns can provide important process information so that the process engineers can identify the key cause of process anomalies. To capture the expert knowledge, the methods in ML/DL are applied extensively such that a robust and long-lasting effect in APC can be established. However, in supervised learning, the manual annotation for wafer map is an extremely exhausting task, and it can also induce the misjudgment when a long-term operation is implemented. This end, this paper proposes a new auto-labeling system based on ensemble classification. The noted VGG16 model is used in ensemble learning as the building block to train the classifier via a limited number of labeled data. Through the model being trained, the auto-labeling procedure is executed to annotate abundant unlabeled data. Therefore, the classification performances between the models trained by supervised and semi-supervised learning can be compared. In addition, the gradient weighted class activation mapping is also adopted to analyze and verify the quality of auto-labeling by visual inspection. The classification performance for wafer defect patterns can be further assured by providing confidence scores of specific defect patterns.