BEC:针对软错误的位级可靠性静态分析

Yousun Ko, Bernd Burgstaller
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摘要

软错误是一种瞬时数字信号损坏,发生在数字硬件组件中,如中央处理器流水线的内部触发器、寄存器文件、内存单元,甚至内部通信总线。软错误由环境放射性、磁干扰、激光和温度波动引起,可能是无意的,也可能是蓄意破坏系统和暴露机密数据的一部分。我们提出了比特级错误聚合(BEC)静态程序分析及其两个用例,以了解和提高程序在软错误面前的可靠性。BEC 分析可跟踪寄存器文件中的每个位损坏,并在编译时根据其语义对损坏的影响进行分类。建议的分析方法在故障注入活动剪枝和可靠性感知程序转换这两种情况下非常有用。实验结果表明,位级分析在不损失准确性的情况下,剪切了多达 30.04% 的详尽故障注入程序(平均为 13.71%)。通过位级漏洞感知指令调度,程序漏洞减少了 13.11%(平均 4.94%)。该分析已在 LLVM 中实现,并在 RISC-V 架构上进行了评估。据我们所知,所提出的 BEC 分析是首个针对软错误的程序可靠性的位级编译器分析。所提出的方法是通用的,并不局限于特定的计算机体系结构。
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BEC: Bit-Level Static Analysis for Reliability against Soft Errors
Soft errors are a type of transient digital signal corruption that occurs in digital hardware components such as the internal flip-flops of CPU pipelines, the register file, memory cells, and even internal communication buses. Soft errors are caused by environmental radioactivity, magnetic interference, lasers, and temperature fluctuations, either unintentionally, or as part of a deliberate attempt to compromise a system and expose confidential data. We propose a bit-level error coalescing (BEC) static program analysis and its two use cases to understand and improve program reliability against soft errors. The BEC analysis tracks each bit corruption in the register file and classifies the effect of the corruption by its semantics at compile time. The usefulness of the proposed analysis is demonstrated in two scenarios, fault injection campaign pruning, and reliability-aware program transformation. Experimental results show that bit-level analysis pruned up to 30.04 % of exhaustive fault injection campaigns (13.71 % on average), without loss of accuracy. Program vulnerability was reduced by up to 13.11 % (4.94 % on average) through bit-level vulnerability-aware instruction scheduling. The analysis has been implemented within LLVM and evaluated on the RISC-V architecture. To the best of our knowledge, the proposed BEC analysis is the first bit-level compiler analysis for program reliability against soft errors. The proposed method is generic and not limited to a specific computer architecture.
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