DANSEN:利用 NDP 在本地计算存储上加速数据库

IF 3.1 4区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE ACM Transactions on Reconfigurable Technology and Systems Pub Date : 2024-04-04 DOI:10.1145/3655625
Sajjad Tamimi, Arthur Bernhardt, Florian Stock, Ilia Petrov, Andreas Koch
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引用次数: 0

摘要

本文介绍了neoDBMS的硬件加速组件DANSEN,这是一个全栈计算存储系统,旨在将数据库查询/交易的设备上执行作为近数据处理(NDP)操作进行管理。该系统可使数据库管理系统(DBMS)将 NDP 操作卸载到存储设备上,同时通过本地存储接口保持对数据的控制。DANSEN 提供的 NDP 引擎可使 DBMS 在智能存储设备上执行数据库管理等低级数据库任务和执行 SQL 等高级任务,同时遵守 DBMS 的并发控制。此外,DANSEN 还能将自定义加速器作为 NDP 操作进行整合,例如直接在存储数据上执行硬件加速的 ML 推理。我们在 Ultrascale+HBM FPGA 上构建了 DANSEN 存储原型和接口,并将其与 PostgreSQL 12 完全集成。实验结果表明,使用快速的现成 NVMe 驱动器,所提出的 NDP 方法优于纯软件 PostgreSQL,并将聚合操作(类似于 CH-benCHmark 中的 Q6,1.5 亿条记录)的端到端执行时间显著提高了 ≈ 10.6 倍。通过将计算密集型数据分析应用与多行结果集成,还验证了所提方法的多功能性,其性能比 PostgreSQL 高出 ≈ 1.5 倍。
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DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP

This paper introduces DANSEN, the hardware accelerator component for neoDBMS, a full-stack computational storage system designed to manage on-device execution of database queries/transactions as a Near-Data Processing (NDP)-operation. The proposed system enables Database Management Systems (DBMS) to offload NDP-operations to the storage while maintaining control over data through a native storage interface. DANSEN provides an NDP-engine that enables DBMS to perform both low-level database tasks, such as performing database administration, as well as high-level tasks like executing SQL, on the smart storage device while observing the DBMS concurrency control. Furthermore, DANSEN enables the incorporation of custom accelerators as an NDP-operation, e.g., to perform hardware-accelerated ML inference directly on the stored data. We built the DANSEN storage prototype and interface on an Ultrascale+HBM FPGA and fully integrated it with PostgreSQL 12. Experimental results demonstrate that the proposed NDP approach outperforms software-only PostgreSQL using a fast off-the-shelf NVMe drive, and significantly improves the end-to-end execution time of an aggregation operation (similar to Q6 from CH-benCHmark, 150 million records) by ≈ 10.6 ×. The versatility of the proposed approach is also validated by integrating a compute-intensive data analytics application with multi-row results, outperforming PostgreSQL by ≈ 1.5 ×.

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来源期刊
ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.90
自引率
8.70%
发文量
79
审稿时长
>12 weeks
期刊介绍: TRETS is the top journal focusing on research in, on, and with reconfigurable systems and on their underlying technology. The scope, rationale, and coverage by other journals are often limited to particular aspects of reconfigurable technology or reconfigurable systems. TRETS is a journal that covers reconfigurability in its own right. Topics that would be appropriate for TRETS would include all levels of reconfigurable system abstractions and all aspects of reconfigurable technology including platforms, programming environments and application successes that support these systems for computing or other applications. -The board and systems architectures of a reconfigurable platform. -Programming environments of reconfigurable systems, especially those designed for use with reconfigurable systems that will lead to increased programmer productivity. -Languages and compilers for reconfigurable systems. -Logic synthesis and related tools, as they relate to reconfigurable systems. -Applications on which success can be demonstrated. The underlying technology from which reconfigurable systems are developed. (Currently this technology is that of FPGAs, but research on the nature and use of follow-on technologies is appropriate for TRETS.) In considering whether a paper is suitable for TRETS, the foremost question should be whether reconfigurability has been essential to success. Topics such as architecture, programming languages, compilers, and environments, logic synthesis, and high performance applications are all suitable if the context is appropriate. For example, an architecture for an embedded application that happens to use FPGAs is not necessarily suitable for TRETS, but an architecture using FPGAs for which the reconfigurability of the FPGAs is an inherent part of the specifications (perhaps due to a need for re-use on multiple applications) would be appropriate for TRETS.
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