UDIR:面向可重构数据流架构的统一编译器框架

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-12-13 DOI:10.1109/LCA.2023.3342130
Nikhil Agarwal;Mitchell Fream;Souradip Ghosh;Brian C. Schwedock;Nathan Beckmann
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引用次数: 0

摘要

与低效的冯-诺依曼内核相比,专用硬件加速器作为一种提高能效的手段,已经获得了广泛的关注。然而,由于专用硬件仅限于少数应用,人们对可编程、非冯-诺依曼架构的兴趣与日俱增,以提高更多程序的效率。可重构数据流架构(RDA)是一种前景广阔的设计,但其设计空间非常分散,尤其是现有的编译器和软件栈都是临时性的,很难使用。如果没有一个强大、成熟的软件生态系统,RDA 与专用硬件相比就会失去很多优势。这封信为 RDA 编译器提出了一种统一的数据流中间表示法(UDIR)。流行的冯-诺依曼编译器表示法不适合数据流架构,因为它们不能表示数据流控制范式,而数据流控制范式是许多常见编译器分析和优化的目标。UDIR 引入了上下文,以打破程序中的指令重用区域。上下文概括了之前的数据流控制范式,代表了程序中必须同步的标记位置。我们在四种先前的数据流架构上对 UDIR 进行了评估,提供了简单的重写规则,将 UDIR 降低到各自特定的机器表示形式,并演示了使用 UDIR 优化内存排序的案例研究。
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UDIR: Towards a Unified Compiler Framework for Reconfigurable Dataflow Architectures
Specialized hardware accelerators have gained traction as a means to improve energy efficiency over inefficient von Neumann cores. However, as specialized hardware is limited to a few applications, there is increasing interest in programmable, non-von Neumann architectures to improve efficiency on a wider range of programs. Reconfigurable dataflow architectures (RDAs) are a promising design, but the design space is fragmented and, in particular, existing compiler and software stacks are ad hoc and hard to use. Without a robust, mature software ecosystem, RDAs lose much of their advantage over specialized hardware. This letter proposes a unifying dataflow intermediate representation (UDIR) for RDA compilers. Popular von Neumann compiler representations are inadequate for dataflow architectures because they do not represent the dataflow control paradigm, which is the target of many common compiler analyses and optimizations. UDIR introduces contexts to break regions of instruction reuse in programs. Contexts generalize prior dataflow control paradigms, representing where in the program tokens must be synchronized. We evaluate UDIR on four prior dataflow architectures, providing simple rewrite rules to lower UDIR to their respective machine-specific representations, and demonstrate a case study of using UDIR to optimize memory ordering.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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