{"title":"热变化环境下异质叠层源双金属 T 型栅隧道场效应晶体管的设计、仿真和模拟/射频性能评估","authors":"Mukesh Kumar, Gautam Bhaskar, Aditya Chotalia, Chhavi Rani, Puja Ghosh, Soumak Nandi, Shashank Kumar Dubey, Kalyan Koley, Aminul Islam","doi":"10.1007/s00542-024-05677-0","DOIUrl":null,"url":null,"abstract":"<p>In this work, a new Hetero-Stacked Source Dual Metal T-shaped Gate Silicon-on-Insulator (SOI) TFET (HS-DMTG-TFET) is proposed, exhibiting significantly improved DC performance, and switching performance over existing TFET topologies. A low threshold voltage of less than 200 mV in the proposed device allows for its integration in a variety of low-power applications. This device has been proposed in response to an acute need for low-power devices for bio-sensing, in situ memory, and loss-minimized switching. The proposed structure incorporates an overlapped gate pocket with a dual metal molybdenum-aluminum gate. The inclusion of a source side pocket improves the tunneling of charge carriers, which enhances the ON-state current. The Band-to-Band-Tunneling (BTBT) characteristic of TG-TFET in a direction perpendicular to the channel contributes to an elevated ON-current, attributed to a comparatively larger tunneling area. The channel exhibits a vertical U-shape, making the proposed device more scalable as compared to existing TFETs. A series of dimension and material-specific optimizations have been made and showcased in this work along with physical reasoning for the observed improvements. An I<sub>ON</sub>/I<sub>OFF</sub> ratio of ~ 10<sup>14</sup> is achieved with an <i>I</i><sub>ON</sub> of 1.05 × 10<sup>–3</sup> A/μm and an <i>I</i><sub>OFF</sub> of 1.35 × 10<sup>–17</sup> A/μm. A highly reduced sub-threshold slope (lower is better) of 10.7 mV/dec is observed, indicating the good transient performance of the device. Considerable improvement in RF performance of the device has been showcased. The temperature dependence on transfer and RF characteristics has been also analyzed. The exhibited device characteristics indicate the potential of using composite material gates for low-power applications over their conventional single-metal counterparts. Reduced power consumption coupled with a compact device structure results in a minimally invasive device, suitable for low-power wearable sensors and bio-integrable circuits.</p>","PeriodicalId":18544,"journal":{"name":"Microsystem Technologies","volume":"18 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design, simulation and analog/RF performance evaluation of a hetero-stacked source dual metal T-shaped gate tunnel-FET in thermally variable environments\",\"authors\":\"Mukesh Kumar, Gautam Bhaskar, Aditya Chotalia, Chhavi Rani, Puja Ghosh, Soumak Nandi, Shashank Kumar Dubey, Kalyan Koley, Aminul Islam\",\"doi\":\"10.1007/s00542-024-05677-0\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>In this work, a new Hetero-Stacked Source Dual Metal T-shaped Gate Silicon-on-Insulator (SOI) TFET (HS-DMTG-TFET) is proposed, exhibiting significantly improved DC performance, and switching performance over existing TFET topologies. A low threshold voltage of less than 200 mV in the proposed device allows for its integration in a variety of low-power applications. This device has been proposed in response to an acute need for low-power devices for bio-sensing, in situ memory, and loss-minimized switching. The proposed structure incorporates an overlapped gate pocket with a dual metal molybdenum-aluminum gate. The inclusion of a source side pocket improves the tunneling of charge carriers, which enhances the ON-state current. The Band-to-Band-Tunneling (BTBT) characteristic of TG-TFET in a direction perpendicular to the channel contributes to an elevated ON-current, attributed to a comparatively larger tunneling area. The channel exhibits a vertical U-shape, making the proposed device more scalable as compared to existing TFETs. A series of dimension and material-specific optimizations have been made and showcased in this work along with physical reasoning for the observed improvements. An I<sub>ON</sub>/I<sub>OFF</sub> ratio of ~ 10<sup>14</sup> is achieved with an <i>I</i><sub>ON</sub> of 1.05 × 10<sup>–3</sup> A/μm and an <i>I</i><sub>OFF</sub> of 1.35 × 10<sup>–17</sup> A/μm. A highly reduced sub-threshold slope (lower is better) of 10.7 mV/dec is observed, indicating the good transient performance of the device. Considerable improvement in RF performance of the device has been showcased. The temperature dependence on transfer and RF characteristics has been also analyzed. The exhibited device characteristics indicate the potential of using composite material gates for low-power applications over their conventional single-metal counterparts. Reduced power consumption coupled with a compact device structure results in a minimally invasive device, suitable for low-power wearable sensors and bio-integrable circuits.</p>\",\"PeriodicalId\":18544,\"journal\":{\"name\":\"Microsystem Technologies\",\"volume\":\"18 1\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-05-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microsystem Technologies\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1007/s00542-024-05677-0\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microsystem Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/s00542-024-05677-0","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design, simulation and analog/RF performance evaluation of a hetero-stacked source dual metal T-shaped gate tunnel-FET in thermally variable environments
In this work, a new Hetero-Stacked Source Dual Metal T-shaped Gate Silicon-on-Insulator (SOI) TFET (HS-DMTG-TFET) is proposed, exhibiting significantly improved DC performance, and switching performance over existing TFET topologies. A low threshold voltage of less than 200 mV in the proposed device allows for its integration in a variety of low-power applications. This device has been proposed in response to an acute need for low-power devices for bio-sensing, in situ memory, and loss-minimized switching. The proposed structure incorporates an overlapped gate pocket with a dual metal molybdenum-aluminum gate. The inclusion of a source side pocket improves the tunneling of charge carriers, which enhances the ON-state current. The Band-to-Band-Tunneling (BTBT) characteristic of TG-TFET in a direction perpendicular to the channel contributes to an elevated ON-current, attributed to a comparatively larger tunneling area. The channel exhibits a vertical U-shape, making the proposed device more scalable as compared to existing TFETs. A series of dimension and material-specific optimizations have been made and showcased in this work along with physical reasoning for the observed improvements. An ION/IOFF ratio of ~ 1014 is achieved with an ION of 1.05 × 10–3 A/μm and an IOFF of 1.35 × 10–17 A/μm. A highly reduced sub-threshold slope (lower is better) of 10.7 mV/dec is observed, indicating the good transient performance of the device. Considerable improvement in RF performance of the device has been showcased. The temperature dependence on transfer and RF characteristics has been also analyzed. The exhibited device characteristics indicate the potential of using composite material gates for low-power applications over their conventional single-metal counterparts. Reduced power consumption coupled with a compact device structure results in a minimally invasive device, suitable for low-power wearable sensors and bio-integrable circuits.