Improved control method of the paralleled three-phase two-level inverters for common-mode voltage and circulating current suppression

The paralleled configuration of three-phase two-level (3P2L) inverters has been put forward to increase the output power rating, operating efficiency, and system reliability. Nevertheless, this architecture brings about the serious circulating current problem, which distorts the quality of output currents, results in additional power losses, and reduces the system efficiency. Another problem is the common-mode voltage (CMV), which causes electromagnetic interference and threatens the safe operation of the system. There exists interconnection between these two issues in the paralleled 3P2L inverters. To suppress the CMV and circulating current simultaneously, an improved control method is presented. At first, the discrete model of paralleled 3P2L inverters is established, based on which the improved control method is designed to restrain the circulating current, while the parameter tuning is avoided. In addition, the zero-sequence component injection associated with the optimized configuration of carrier phase is conducted, and the CMV magnitude of each inverter is limited within one-sixth of dc-side voltage. When comparing with the traditional space vector modulation (SVM) approach, the CMV magnitude is restrained by two-thirds by the presented method. The hardware-based evaluation results have been provided to validate the presented approach.