面向高能效 LLM 推理服务的 SLO 感知 GPU DVFS

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-03-28 DOI:10.1109/LCA.2024.3406038
Andreas Kosmas Kakolyris;Dimosthenis Masouros;Sotirios Xydis;Dimitrios Soudris
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引用次数: 0

摘要

基于 LLM 的聊天机器人越来越受欢迎,再加上它们对耗电的 GPU 基础设施的依赖,给提供商带来了严峻的挑战:如何在确保最佳用户体验的服务级别目标(SLO)下最大限度地降低能耗。传统的能耗优化方法由于其自回归架构而无法满足预定义的 SLO,从而导致能耗超配,因此无法满足 LLM 推理的要求。不过,这种自回归特性允许进行迭代级调整,从而在整个推理过程中对系统进行持续微调。在这封信中,我们提出了一种基于迭代级 GPU 动态电压频率缩放(DVFS)的解决方案,旨在减少 LLM 服务对能源的影响,这种方法在不同 SLO 约束条件下的实际情况中进行测试时,有可能实现超过 22.8%、最多 45.5% 的能源增益。我们的方法可在现有 LLM 托管服务的基础上运行,只需最低限度的剖析,无需干预推理服务系统。
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SLO-Aware GPU DVFS for Energy-Efficient LLM Inference Serving
The increasing popularity of LLM-based chatbots combined with their reliance on power-hungry GPU infrastructure forms a critical challenge for providers: minimizing energy consumption under Service-Level Objectives (SLOs) that ensure optimal user experience. Traditional energy optimization methods fall short for LLM inference due to their autoregressive architecture, which renders them incapable of meeting a predefined SLO without energy overprovisioning . This autoregressive nature however, allows for iteration-level adjustments, enabling continuous fine-tuning of the system throughout the inference process. In this letter, we propose a solution based on iteration-level GPU Dynamic Voltage Frequency Scaling (DVFS), aiming to reduce the energy impact of LLM serving, an approach that has the potential for more than 22.8% and up to 45.5% energy gains when tested in real world situations under varying SLO constraints. Our approach works on top of existing LLM hosting services, requires minimal profiling and no intervention to the inference serving system.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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