具有最小 TTD 的多位抗错 FPGA Cram

B. Kala, D. Arulanantham
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引用次数: 0

摘要

在太空等恶劣环境中,辐射和带电粒子会导致单事件和多位效应,即在任何电子元件上随机发生的故障。这些故障必须得到缓解,以确保设备的功能。现代的缓解方法,如三重模块冗余,对单次瞬变(SET)非常有效,但在面积上至少需要 3 倍的成本。单事件瞬变(SEU)会影响顺序元素,并定期使用内存擦除进行修复。擦除是一个缓慢的串行过程,通过每个内存字查找要修复的错误。在修复之前,需要花费不可忽略的检测时间(TTD),在此期间可能会发生其他事件并危及系统。现场可编程门阵列 (FPGA) 在很大程度上依赖于顺序元素来存储配置;因此,FPGA 的 SEU 检测时间对于在恶劣条件下确保设计完整性至关重要。这就需要一个强大的纠错码(ECC)来保护电子设备免受 MCU 的影响。本文介绍了使用矩阵代码检测和纠正 FPGA 配置存储器中多重错误的新算法的构思、实施和评估。带有奇偶校验位的多位段组合架构有助于定位和纠正双三位错误。所提出的方法允许异步 MEU 检测,并用固定的 TTD 代替了擦除检测的可变时间。与现有方法相比,基于矩阵代码的 IMECCC 减少了 FPGA 的 TTD。
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Multi-Bit Error Resilient FPGA Cram with Minimum TTD
In harsh environments such as space, radiation and charged particles cause Single-Event and Multi-bit Effects, faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy, are very effective against Single Event Transients (SETs), but incur a minimum of 3× cost in area. Single-Event Upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process, going through every memory word looking for errors to repair. It involves a non-negligible Time to Detect (TTD) before repair, during which other events can occur and compromise the system. Field Programmable Gate Arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design integrity in harsh conditions. It is required a robust error correction code (ECC) to protect electronic devices from MCUs. The proposed work describes the conception, implementation and evaluation of new algorithm using matrix code for the detection and correction of multiple errors in FPGA configuration memories. The combined architecture with multiple bit segment with parity bits helps in locating and correcting double-triple bit errors. The proposed Method allows asynchronous MEU detection and replaces scrubbing variable time to detect with a fixed TTD. The IMECCC based on Matrix code reduces FPGA’s TTD compared to existing method.
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