用于射频应用的互耦双级 RC 反馈低噪声放大器

Manish Kumar, Dheeraj Kalra, Aasheesh Shukla
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摘要

摘要 所设计的电路采用双级低噪声放大器(LNA),其中共源(CS)配置可实现高增益,而后级采用互补共门(CCG)设置可实现低功耗。这种配置可确保两个晶体管共享相同的偏置电流,从而提高能效。这两级以级联配置相互连接,从而放大了整体增益,同时降低了噪声。为促进输入级的宽带匹配,采用了并行 RC 反馈机制。此外,CS 级和 CCG 级中的一对相互耦合的电感器有助于使输入阻抗完全电阻化,同时最大限度地减小电路的整体尺寸。所有仿真均采用 65 纳米 CMOS 技术,在 Cadence Virtuoso 中完成。该 LNA 的噪声系数 (NF) 为 3.2 dB,峰值功率增益 (S21) 为 19.8 dB,输入反射系数 (S11) 为 -16.2 dB,带宽为 3.1-6.2 GHz。该 LNA 采用 1V 电源供电,功耗仅为 2.8 mW,具有很高的能效。该 LNA 的整体性能评估采用了 "优越性图"(Figure of Merit),得出的数值为 18.2。与其他先进设计的比较分析见表 1。
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Mutually coupled dual-stage RC feedback LNA for RF applications
Abstract The designed circuit features a dual-stage Low Noise Amplifier (LNA) in which, a common source (CS) configuration is employed to achieve high gain, while the subsequent stage adopts a Complementary Common Gate (CCG) setup provide the low power consumption. This arrangement ensures that both transistors share the same biasing current, promoting energy efficiency. The two stages are interconnected in a cascade configuration, amplifying the overall gain and concurrently mitigating noise. To facilitate wideband matching in the input stage, a parallel RC feedback mechanism is implemented. Additionally, a pair of mutually coupled inductors in the CS and CCG stages contribute to rendering the input impedance exclusively resistive, concurrently minimizing the overall size of the circuit. All simulations were done using 65 nm CMOS technology in Cadence Virtuoso. The proposed LNA showcases a Noise Figure (NF) of 3.2 dB, a Peak Power Gain (S21) of 19.8 dB, and an input reflection coefficient (S11) of –16.2 dB, spanning a bandwidth of 3.1-6.2 GHz. Operating on a 1V power supply, the proposed LNA demonstrates power efficiency by consuming only 2.8 mW. The overall performance assessment of the LNA is gauged using the Figure of Merit, yielding an obtained value of 18.2. Comparative analysis with other cutting-edge designs is presented in Table 1.
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