Robust design of phase-locked loops in grid-connected power converters

Phase-locked loop (PLL) algorithms are key elements for the successful integration of converter-interfaced renewable energy sources to the grid. Their main task is to estimate the phase angle of the terminal grid voltage with the aim to keep the converter output current synchronized to it. Yet, due to the increasing penetration of power-electronics-interfaced devices in power systems, the grid voltage signal becomes increasingly disturbed, making the reliable phase estimation a highly demanding task. To address this challenge, we present a robust design method based on matrix inequalities to tune the PLL gains, such that the estimation errors remain bounded in the presence of additive disturbances. Our design approach is formulated as a set of bilinear matrix inequalities (BMIs), which we then propose to solve using the P-K iteration method. This results in a convex problem to be solved at each step. Finally, the benefits of the proposed robust design are illustrated via a numerical example.