{"title":"通过 CXL 分解内存的编程模型","authors":"Gal Assa, Michal Friedman, Ori Lahav","doi":"arxiv-2407.16300","DOIUrl":null,"url":null,"abstract":"CXL (Compute Express Link) is an emerging open industry-standard interconnect\nbetween processing and memory devices that is expected to revolutionize the way\nsystems are designed in the near future. It enables cache-coherent shared\nmemory pools in a disaggregated fashion at unprecedented scales, allowing\nalgorithms to interact with a variety of storage devices using simple loads and\nstores in a cacheline granularity. Alongside with unleashing unique\nopportunities for a wide range of applications, CXL introduces new challenges\nof data management and crash consistency. Alas, CXL lacks an adequate\nprogramming model, which makes reasoning about the correctness and expected\nbehaviors of algorithms and systems on top of it nearly impossible. In this work, we present CXL0, the first programming model for concurrent\nprograms running on top of CXL. We propose a high-level abstraction for CXL\nmemory accesses and formally define operational semantics on top of that\nabstraction. We provide a set of general transformations that adapt concurrent\nalgorithms to the new disruptive technology. Using these transformations, every\nlinearizable algorithm can be easily transformed into its provably correct\nversion in the face of a full-system or sub-system crash. We believe that this\nwork will serve as the stepping stone for systems design and modelling on top\nof CXL, and support the development of future models as software and hardware\nevolve.","PeriodicalId":501168,"journal":{"name":"arXiv - CS - Emerging Technologies","volume":"29 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Programming Model for Disaggregated Memory over CXL\",\"authors\":\"Gal Assa, Michal Friedman, Ori Lahav\",\"doi\":\"arxiv-2407.16300\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"CXL (Compute Express Link) is an emerging open industry-standard interconnect\\nbetween processing and memory devices that is expected to revolutionize the way\\nsystems are designed in the near future. It enables cache-coherent shared\\nmemory pools in a disaggregated fashion at unprecedented scales, allowing\\nalgorithms to interact with a variety of storage devices using simple loads and\\nstores in a cacheline granularity. Alongside with unleashing unique\\nopportunities for a wide range of applications, CXL introduces new challenges\\nof data management and crash consistency. Alas, CXL lacks an adequate\\nprogramming model, which makes reasoning about the correctness and expected\\nbehaviors of algorithms and systems on top of it nearly impossible. In this work, we present CXL0, the first programming model for concurrent\\nprograms running on top of CXL. We propose a high-level abstraction for CXL\\nmemory accesses and formally define operational semantics on top of that\\nabstraction. We provide a set of general transformations that adapt concurrent\\nalgorithms to the new disruptive technology. Using these transformations, every\\nlinearizable algorithm can be easily transformed into its provably correct\\nversion in the face of a full-system or sub-system crash. We believe that this\\nwork will serve as the stepping stone for systems design and modelling on top\\nof CXL, and support the development of future models as software and hardware\\nevolve.\",\"PeriodicalId\":501168,\"journal\":{\"name\":\"arXiv - CS - Emerging Technologies\",\"volume\":\"29 1\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-07-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"arXiv - CS - Emerging Technologies\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/arxiv-2407.16300\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"arXiv - CS - Emerging Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/arxiv-2407.16300","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Programming Model for Disaggregated Memory over CXL
CXL (Compute Express Link) is an emerging open industry-standard interconnect
between processing and memory devices that is expected to revolutionize the way
systems are designed in the near future. It enables cache-coherent shared
memory pools in a disaggregated fashion at unprecedented scales, allowing
algorithms to interact with a variety of storage devices using simple loads and
stores in a cacheline granularity. Alongside with unleashing unique
opportunities for a wide range of applications, CXL introduces new challenges
of data management and crash consistency. Alas, CXL lacks an adequate
programming model, which makes reasoning about the correctness and expected
behaviors of algorithms and systems on top of it nearly impossible. In this work, we present CXL0, the first programming model for concurrent
programs running on top of CXL. We propose a high-level abstraction for CXL
memory accesses and formally define operational semantics on top of that
abstraction. We provide a set of general transformations that adapt concurrent
algorithms to the new disruptive technology. Using these transformations, every
linearizable algorithm can be easily transformed into its provably correct
version in the face of a full-system or sub-system crash. We believe that this
work will serve as the stepping stone for systems design and modelling on top
of CXL, and support the development of future models as software and hardware
evolve.