Efficient hardware design of spiking neurons and unsupervised learning module in large scale pattern classification network

The main interest of high-precision, low-energy computing in machines with superior intelligence capabilities is to improve the performance of biologically spiking neural networks (SNNs). In this paper, we address this by presenting a new power-law update of synaptic weights based on burst time-dependent plasticity (Pow-BTDP) as a digital learning block in a SNN model with multiplier-less neuron modules. Propelled by the request for accurate and fast computations that diminishes costly resources in neural network applications, this paper introduces an efficient hardware methodology based on linear approximations. The presented hardware designs based on linear approximation of non-linear terms in learning module (exponential and fractional power) and neuron blocks (second power) are carefully elaborated to guarantee optimal speedup, low resource consumption, and accuracy. The architectures developed for Exp and Power implementations are illustrated and evaluated, leading to the presentation of digital learning module and neuron block that enable efficient and accurate hardware computation. The proposed digital modules of learning mechanism and neuron was used to construct large scale event-based spiking neural network comprising of three layers, enabling unsupervised training with variable learning rate utilizing excitatory and inhibitory neural connections. As a results, the proposed bio-inspired SNN as a spiking pattern classification network with the proposed Pow-BTDP learning approach, by training on MNIST, EMNIST digits, EMNIST letters, and CIFAR10 datasets with respectively 6, 2, 2 and 6 training epochs, achieved superior accuracy 97.9%, 97.8%, 94.2%, and 93.3% which indicate higher accuracy and convergence speed compare to previous works.