{"title":"PatternPaint:使用生成式人工智能和内绘技术生成布局图案","authors":"Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy, Jiang Hu, Yiran Chen, Dipto G. Thakurta","doi":"arxiv-2409.01348","DOIUrl":null,"url":null,"abstract":"Generation of VLSI layout patterns is essential for a wide range of Design\nFor Manufacturability (DFM) studies. In this study, we investigate the\npotential of generative machine learning models for creating design rule legal\nmetal layout patterns. Our results demonstrate that the proposed model can\ngenerate legal patterns in complex design rule settings and achieves a high\ndiversity score. The designed system, with its flexible settings, supports both\npattern generation with localized changes, and design rule violation\ncorrection. Our methodology is validated on Intel 18A Process Design Kit (PDK)\nand can produce a wide range of DRC-compliant pattern libraries with only 20\nstarter patterns.","PeriodicalId":501309,"journal":{"name":"arXiv - CS - Computational Engineering, Finance, and Science","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"PatternPaint: Generating Layout Patterns Using Generative AI and Inpainting Techniques\",\"authors\":\"Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy, Jiang Hu, Yiran Chen, Dipto G. Thakurta\",\"doi\":\"arxiv-2409.01348\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Generation of VLSI layout patterns is essential for a wide range of Design\\nFor Manufacturability (DFM) studies. In this study, we investigate the\\npotential of generative machine learning models for creating design rule legal\\nmetal layout patterns. Our results demonstrate that the proposed model can\\ngenerate legal patterns in complex design rule settings and achieves a high\\ndiversity score. The designed system, with its flexible settings, supports both\\npattern generation with localized changes, and design rule violation\\ncorrection. Our methodology is validated on Intel 18A Process Design Kit (PDK)\\nand can produce a wide range of DRC-compliant pattern libraries with only 20\\nstarter patterns.\",\"PeriodicalId\":501309,\"journal\":{\"name\":\"arXiv - CS - Computational Engineering, Finance, and Science\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-09-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"arXiv - CS - Computational Engineering, Finance, and Science\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/arxiv-2409.01348\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"arXiv - CS - Computational Engineering, Finance, and Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/arxiv-2409.01348","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
PatternPaint: Generating Layout Patterns Using Generative AI and Inpainting Techniques
Generation of VLSI layout patterns is essential for a wide range of Design
For Manufacturability (DFM) studies. In this study, we investigate the
potential of generative machine learning models for creating design rule legal
metal layout patterns. Our results demonstrate that the proposed model can
generate legal patterns in complex design rule settings and achieves a high
diversity score. The designed system, with its flexible settings, supports both
pattern generation with localized changes, and design rule violation
correction. Our methodology is validated on Intel 18A Process Design Kit (PDK)
and can produce a wide range of DRC-compliant pattern libraries with only 20
starter patterns.