Stress-induced warpage estimation of advanced semiconductor copper interconnect processes

The growth of the semiconductor industry is driven by the demand for electronic products and high transistor density. However, complex manufacturing processes generate residual stress and result in wafer warpage. Therefore, mastering wafer warpage has become a crucial challenge. This study proposes a process-oriented simulation methodology with simulation-based equivalent material method to overcome the difficulty of finite element modeling and the substantial amount of computation time. Three different methodologies, including volume percentage, representative volume element, and Timoshenko bi-material approach, are discussed due to the estimation of residual stress for equivalent material. In addition, each methodology is validated through process-oriented simulations and comparison with measurement data. The Timoshenko bi-material approach is efficient in predicting warpage in the back end of line (BEOL) interconnects and provides a comprehensive understanding of the warpage variation that occurs during different stages of BEOL.