基于顶层金属和 C4 平面螺旋电感器的单片式、10.5 W/mm$^{2}$、600 MHz、16 nm 级集成降压稳压器

IF 5.6 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-10-03 DOI:10.1109/JSSC.2024.3464448

Suhwan Kim;Harish K. Krishnamurthy;Zakir K. Ahmed;Nachiket Desai;Sheldon Weng;Anne E. Augustine;Huong T. Do;Jingshu Yu;Phong D. Bach;Xiaosen Liu;Kaladhar Radhakrishnan;Krishnan Ravichandran;James W. Tschanz;Vivek De

{"title":"基于顶层金属和 C4 平面螺旋电感器的单片式、10.5 W/mm$^{2}$、600 MHz、16 nm 级集成降压稳压器","authors":"Suhwan Kim;Harish K. Krishnamurthy;Zakir K. Ahmed;Nachiket Desai;Sheldon Weng;Anne E. Augustine;Huong T. Do;Jingshu Yu;Phong D. Bach;Xiaosen Liu;Kaladhar Radhakrishnan;Krishnan Ravichandran;James W. Tschanz;Vivek De","doi":"10.1109/JSSC.2024.3464448","DOIUrl":null,"url":null,"abstract":"A monolithic buck voltage regulator (VR) built with top-metal and industry-first C4 planar spiral inductors demonstrates 2.5 times higher power density than prior art, providing efficient alternative to low-dropout linear regulators (LDOs) powering disaggregated digital, IO and PHY IPs. The 1.1 V single-stack power stage, DPWM delay-line, self-triggered windowed-flash ADC, and fully digital and reconfigurable controller are designed for high frequency, delivering 10.5 W/mm2 at 600 MHz, with 0.35–0.85 V operating range and 18%–25% improvement in efficiency over an ideal LDO.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 1","pages":"75-84"},"PeriodicalIF":5.6000,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Monolithic, 10.5 W/mm2, 600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16 nm Class\",\"authors\":\"Suhwan Kim;Harish K. Krishnamurthy;Zakir K. Ahmed;Nachiket Desai;Sheldon Weng;Anne E. Augustine;Huong T. Do;Jingshu Yu;Phong D. Bach;Xiaosen Liu;Kaladhar Radhakrishnan;Krishnan Ravichandran;James W. Tschanz;Vivek De\",\"doi\":\"10.1109/JSSC.2024.3464448\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A monolithic buck voltage regulator (VR) built with top-metal and industry-first C4 planar spiral inductors demonstrates 2.5 times higher power density than prior art, providing efficient alternative to low-dropout linear regulators (LDOs) powering disaggregated digital, IO and PHY IPs. The 1.1 V single-stack power stage, DPWM delay-line, self-triggered windowed-flash ADC, and fully digital and reconfigurable controller are designed for high frequency, delivering 10.5 W/mm2 at 600 MHz, with 0.35–0.85 V operating range and 18%–25% improvement in efficiency over an ideal LDO.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"60 1\",\"pages\":\"75-84\"},\"PeriodicalIF\":5.6000,\"publicationDate\":\"2024-10-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10702606/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10702606/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

采用顶级金属和行业领先的C4平面螺旋电感构建的单片降压稳压器（VR）具有比现有技术高2.5倍的功率密度，为分散的数字、IO和PHY ip提供低差线性稳压器（ldo）的有效替代方案。1.1 V单堆叠功率级、DPWM延迟线、自触发加窗闪光ADC和全数字和可重构控制器专为高频设计，在600 MHz时输出10.5 W/mm2，工作范围为0.35-0.85 V，效率比理想的LDO提高18%-25%。

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A Monolithic, 10.5 W/mm2, 600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16 nm Class

A monolithic buck voltage regulator (VR) built with top-metal and industry-first C4 planar spiral inductors demonstrates 2.5 times higher power density than prior art, providing efficient alternative to low-dropout linear regulators (LDOs) powering disaggregated digital, IO and PHY IPs. The 1.1 V single-stack power stage, DPWM delay-line, self-triggered windowed-flash ADC, and fully digital and reconfigurable controller are designed for high frequency, delivering 10.5 W/mm2 at 600 MHz, with 0.35–0.85 V operating range and 18%–25% improvement in efficiency over an ideal LDO.

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来源期刊

IEEE Journal of Solid-state Circuits 工程技术-工程：电子与电气

CiteScore

11.00

自引率

20.40%

发文量

351

审稿时长

3-6 weeks

期刊介绍： The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.

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