An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips

This article presents a novel integer-floating-point (INT-FP) gain-cell (GC)-computing-in-memory (CIM) structure for high-precision multiply-and-accumulate (MAC) operations with high computational flexibility, energy efficiency, and inference accuracy. The proposed device employs: 1) a dual-mode zone-based input processing scheme (ZB-IPS) aimed at eliminating exponent subtraction in order to enhance energy and area efficiency (AEF); 2) a dual-mode local computing cell (DM-LCC) to reuse exponent addition as an adder tree stage for INT-MAC to enhance AEF in both INT and floating-point (FP) modes; and 3) a stationary-based two-port GC array (SB-TP-GCA) to enable concurrent data updates and computation while reducing system-to-CIM and internal data accesses to improve energy efficiency. A 16-nm FinFET 108-kb GC-CIM macro fabricated using 4T gain cells (GCs) achieved energy efficiency of 99.5 TOPS/W in INT-MAC operations involving 128 accumulations of 8b-input, 8b-weight, and 23b-output; and 46.4 TFLOPS/W in FP-MAC operations involving 64 accumulations of BF16-input, BF16-weight, and FP32-output.