{"title":"基于单端紧凑型结块 L-C-L 和差分耦合线嵌入网络、采用宽带 $G_\\text{max}$ 内核的 150-GHz 单变差 LNA","authors":"Hokeun Lee;Hyo-Ryeong Jeon;Sang-Gug Lee;Kyung-Sik Choi","doi":"10.1109/JSSC.2024.3474008","DOIUrl":null,"url":null,"abstract":"This work presents a high-gain and wideband 150-GHz LNA featuring a single-to-differential (S2D) topology. The S2D topology eliminates the need for a lossy balun in the input matching network, resulting in an inherent improvement of the achievable noise figure (NF). The proposed four-stage LNA is implemented based on high-gain and wideband <inline-formula> <tex-math>$G_{\\max }$ </tex-math></inline-formula>-cores. For a compact realization, the first-stage single-ended (SE) <inline-formula> <tex-math>$G_{\\max }$ </tex-math></inline-formula>-core uses lumped elements (<italic>L</i>-<italic>C</i>-<italic>L</i>) within its embedding network. In addition, a pseudo-simultaneous noise and input matching (p-SNIM) technique is used to mitigate the tradeoff between gain and noise characteristics. Differential wideband <inline-formula> <tex-math>$G_{\\max }$ </tex-math></inline-formula>-cores in the subsequent stages use a coupled-line-based embedding network (CLEN) without any explicit capacitors. It helps simplify the dc biasing and generally enhances the tolerance to process variations with a compact form factor. Implemented in a 40-nm CMOS technology, the proposed LNA achieves a peak power gain of 20.0 dB, a 3-dB bandwidth of 18.8 GHz, a minimum NF of 4.9 dB, and a maximum OP<sub>1dB</sub>/IP<sub>1dB</sub> of −7.7/−22.4 dBm, respectively, while dissipating dc power of 19.6 mW. To the authors’ best knowledge, this work is the first implementation of an S2D LNA operating above 100 GHz using CMOS technologies.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 6","pages":"1973-1984"},"PeriodicalIF":5.6000,"publicationDate":"2024-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 150-GHz Single-to-Differential LNA Adopting Wideband Gmax-Cores Based on Single-Ended Compact Lumped L-C-L and Differential Coupled-Line Embedding Networks\",\"authors\":\"Hokeun Lee;Hyo-Ryeong Jeon;Sang-Gug Lee;Kyung-Sik Choi\",\"doi\":\"10.1109/JSSC.2024.3474008\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a high-gain and wideband 150-GHz LNA featuring a single-to-differential (S2D) topology. The S2D topology eliminates the need for a lossy balun in the input matching network, resulting in an inherent improvement of the achievable noise figure (NF). The proposed four-stage LNA is implemented based on high-gain and wideband <inline-formula> <tex-math>$G_{\\\\max }$ </tex-math></inline-formula>-cores. For a compact realization, the first-stage single-ended (SE) <inline-formula> <tex-math>$G_{\\\\max }$ </tex-math></inline-formula>-core uses lumped elements (<italic>L</i>-<italic>C</i>-<italic>L</i>) within its embedding network. In addition, a pseudo-simultaneous noise and input matching (p-SNIM) technique is used to mitigate the tradeoff between gain and noise characteristics. Differential wideband <inline-formula> <tex-math>$G_{\\\\max }$ </tex-math></inline-formula>-cores in the subsequent stages use a coupled-line-based embedding network (CLEN) without any explicit capacitors. It helps simplify the dc biasing and generally enhances the tolerance to process variations with a compact form factor. Implemented in a 40-nm CMOS technology, the proposed LNA achieves a peak power gain of 20.0 dB, a 3-dB bandwidth of 18.8 GHz, a minimum NF of 4.9 dB, and a maximum OP<sub>1dB</sub>/IP<sub>1dB</sub> of −7.7/−22.4 dBm, respectively, while dissipating dc power of 19.6 mW. To the authors’ best knowledge, this work is the first implementation of an S2D LNA operating above 100 GHz using CMOS technologies.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"60 6\",\"pages\":\"1973-1984\"},\"PeriodicalIF\":5.6000,\"publicationDate\":\"2024-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10720034/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10720034/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 150-GHz Single-to-Differential LNA Adopting Wideband Gmax-Cores Based on Single-Ended Compact Lumped L-C-L and Differential Coupled-Line Embedding Networks
This work presents a high-gain and wideband 150-GHz LNA featuring a single-to-differential (S2D) topology. The S2D topology eliminates the need for a lossy balun in the input matching network, resulting in an inherent improvement of the achievable noise figure (NF). The proposed four-stage LNA is implemented based on high-gain and wideband $G_{\max }$ -cores. For a compact realization, the first-stage single-ended (SE) $G_{\max }$ -core uses lumped elements (L-C-L) within its embedding network. In addition, a pseudo-simultaneous noise and input matching (p-SNIM) technique is used to mitigate the tradeoff between gain and noise characteristics. Differential wideband $G_{\max }$ -cores in the subsequent stages use a coupled-line-based embedding network (CLEN) without any explicit capacitors. It helps simplify the dc biasing and generally enhances the tolerance to process variations with a compact form factor. Implemented in a 40-nm CMOS technology, the proposed LNA achieves a peak power gain of 20.0 dB, a 3-dB bandwidth of 18.8 GHz, a minimum NF of 4.9 dB, and a maximum OP1dB/IP1dB of −7.7/−22.4 dBm, respectively, while dissipating dc power of 19.6 mW. To the authors’ best knowledge, this work is the first implementation of an S2D LNA operating above 100 GHz using CMOS technologies.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.