基于单端紧凑型结块 L-C-L 和差分耦合线嵌入网络、采用宽带 $G_\text{max}$ 内核的 150-GHz 单变差 LNA

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-10-16 DOI:10.1109/JSSC.2024.3474008
Hokeun Lee;Hyo-Ryeong Jeon;Sang-Gug Lee;Kyung-Sik Choi
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引用次数: 0

摘要

这项工作提出了一种具有单对差分(S2D)拓扑结构的高增益和宽带150 ghz LNA。S2D拓扑消除了输入匹配网络中对有损平衡的需要,从而固有地改善了可实现的噪声系数(NF)。所提出的四级LNA是基于高增益和宽带的$G_{\max}$ -内核实现的。为了紧凑的实现,第一阶段单端(SE) $G_{\max}$ -core在其嵌入网络中使用集总元素(L-C-L)。此外,伪同步噪声和输入匹配(p-SNIM)技术用于减轻增益和噪声特性之间的权衡。后续阶段的差分宽带$G_{\max}$ -内核使用基于耦合线的嵌入网络(CLEN),没有任何显式电容器。它有助于简化直流偏置,并通过紧凑的外形因素增强对工艺变化的容忍度。该LNA采用40nm CMOS技术实现,峰值功率增益为20.0 dB, 3db带宽为18.8 GHz,最小NF为4.9 dB,最大OP1dB/IP1dB分别为−7.7/−22.4 dBm,直流功耗为19.6 mW。据作者所知,这项工作是首次使用CMOS技术实现工作在100 GHz以上的S2D LNA。
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A 150-GHz Single-to-Differential LNA Adopting Wideband Gmax-Cores Based on Single-Ended Compact Lumped L-C-L and Differential Coupled-Line Embedding Networks
This work presents a high-gain and wideband 150-GHz LNA featuring a single-to-differential (S2D) topology. The S2D topology eliminates the need for a lossy balun in the input matching network, resulting in an inherent improvement of the achievable noise figure (NF). The proposed four-stage LNA is implemented based on high-gain and wideband $G_{\max }$ -cores. For a compact realization, the first-stage single-ended (SE) $G_{\max }$ -core uses lumped elements (L-C-L) within its embedding network. In addition, a pseudo-simultaneous noise and input matching (p-SNIM) technique is used to mitigate the tradeoff between gain and noise characteristics. Differential wideband $G_{\max }$ -cores in the subsequent stages use a coupled-line-based embedding network (CLEN) without any explicit capacitors. It helps simplify the dc biasing and generally enhances the tolerance to process variations with a compact form factor. Implemented in a 40-nm CMOS technology, the proposed LNA achieves a peak power gain of 20.0 dB, a 3-dB bandwidth of 18.8 GHz, a minimum NF of 4.9 dB, and a maximum OP1dB/IP1dB of −7.7/−22.4 dBm, respectively, while dissipating dc power of 19.6 mW. To the authors’ best knowledge, this work is the first implementation of an S2D LNA operating above 100 GHz using CMOS technologies.
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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