Su-Hyun Han;Seonghyeok Park;Jung-Hoon Chun;Jaehyuk Choi;Seong-Jin Kim
{"title":"用于闪光激光雷达传感器的 35-$\\mu$m 像素间距的 3.1-$\\mu$W 模拟辅助变焦直方图 TDC","authors":"Su-Hyun Han;Seonghyeok Park;Jung-Hoon Chun;Jaehyuk Choi;Seong-Jin Kim","doi":"10.1109/JSSC.2024.3474830","DOIUrl":null,"url":null,"abstract":"This article presents a CMOS flash light detection and ranging (LiDAR) sensor featuring an analog-assisted in-pixel zoom histogramming time-to-digital converter (hTDC) to pave the way for realizing an area- and energy-efficient architecture. The proposed hTDC substitutes digital counters and logic in the timing generator (TG) in the previous hTDC with analog counterparts comprising a time-to-analog converter (TAC) and a self-referenced successive approximation register analog-to-digital converter (SAR ADC). It supports the two-step zoom hTDC functionality based on the SA-hTDC for the coarse step and the indirect time-of-flight (iToF) technique for the fine step. The proposed architecture minimizes the need for high-frequency clocks, resulting in an impressively low pixel power consumption of <inline-formula> <tex-math>$3.1~{\\mu }$ </tex-math></inline-formula>W per pixel. In addition, by placing the capacitors underneath the SPAD device, the pixel pitch is scaled down to <inline-formula> <tex-math>$35~{\\mu }$ </tex-math></inline-formula>m. The self-referenced SAR ADC mitigates PVT variations in the analog TG and suppresses the pixel-to-pixel nonuniformities in the conversion slope of the TAC. The D-latches in the depth memory are repurposed to store and read the 4-b coarse ToF sequentially and the 10-b digital output of the single-slope (SS) ADC from the fine operation. The prototype LiDAR sensor with a <inline-formula> <tex-math>$160 {\\times } 120$ </tex-math></inline-formula> pixel array was fabricated in a 0.11-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m CMOS image sensor (CIS) process. The coarse TDC offers a resolution of 1.5 m, providing a detection range of up to 24 m. The coarse and fine TDC measures a depth accuracy of 2.9 cm and precision of 3.5 cm, respectively, within a range of 3–4.4 m.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 6","pages":"2134-2145"},"PeriodicalIF":5.6000,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 3.1-μW Analog-Assisted Zoom Histogramming TDC in 35-μm Pixel Pitch for Flash LiDAR Sensor\",\"authors\":\"Su-Hyun Han;Seonghyeok Park;Jung-Hoon Chun;Jaehyuk Choi;Seong-Jin Kim\",\"doi\":\"10.1109/JSSC.2024.3474830\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents a CMOS flash light detection and ranging (LiDAR) sensor featuring an analog-assisted in-pixel zoom histogramming time-to-digital converter (hTDC) to pave the way for realizing an area- and energy-efficient architecture. The proposed hTDC substitutes digital counters and logic in the timing generator (TG) in the previous hTDC with analog counterparts comprising a time-to-analog converter (TAC) and a self-referenced successive approximation register analog-to-digital converter (SAR ADC). It supports the two-step zoom hTDC functionality based on the SA-hTDC for the coarse step and the indirect time-of-flight (iToF) technique for the fine step. The proposed architecture minimizes the need for high-frequency clocks, resulting in an impressively low pixel power consumption of <inline-formula> <tex-math>$3.1~{\\\\mu }$ </tex-math></inline-formula>W per pixel. In addition, by placing the capacitors underneath the SPAD device, the pixel pitch is scaled down to <inline-formula> <tex-math>$35~{\\\\mu }$ </tex-math></inline-formula>m. The self-referenced SAR ADC mitigates PVT variations in the analog TG and suppresses the pixel-to-pixel nonuniformities in the conversion slope of the TAC. The D-latches in the depth memory are repurposed to store and read the 4-b coarse ToF sequentially and the 10-b digital output of the single-slope (SS) ADC from the fine operation. The prototype LiDAR sensor with a <inline-formula> <tex-math>$160 {\\\\times } 120$ </tex-math></inline-formula> pixel array was fabricated in a 0.11-<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m CMOS image sensor (CIS) process. The coarse TDC offers a resolution of 1.5 m, providing a detection range of up to 24 m. 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A 3.1-μW Analog-Assisted Zoom Histogramming TDC in 35-μm Pixel Pitch for Flash LiDAR Sensor
This article presents a CMOS flash light detection and ranging (LiDAR) sensor featuring an analog-assisted in-pixel zoom histogramming time-to-digital converter (hTDC) to pave the way for realizing an area- and energy-efficient architecture. The proposed hTDC substitutes digital counters and logic in the timing generator (TG) in the previous hTDC with analog counterparts comprising a time-to-analog converter (TAC) and a self-referenced successive approximation register analog-to-digital converter (SAR ADC). It supports the two-step zoom hTDC functionality based on the SA-hTDC for the coarse step and the indirect time-of-flight (iToF) technique for the fine step. The proposed architecture minimizes the need for high-frequency clocks, resulting in an impressively low pixel power consumption of $3.1~{\mu }$ W per pixel. In addition, by placing the capacitors underneath the SPAD device, the pixel pitch is scaled down to $35~{\mu }$ m. The self-referenced SAR ADC mitigates PVT variations in the analog TG and suppresses the pixel-to-pixel nonuniformities in the conversion slope of the TAC. The D-latches in the depth memory are repurposed to store and read the 4-b coarse ToF sequentially and the 10-b digital output of the single-slope (SS) ADC from the fine operation. The prototype LiDAR sensor with a $160 {\times } 120$ pixel array was fabricated in a 0.11-$\mu $ m CMOS image sensor (CIS) process. The coarse TDC offers a resolution of 1.5 m, providing a detection range of up to 24 m. The coarse and fine TDC measures a depth accuracy of 2.9 cm and precision of 3.5 cm, respectively, within a range of 3–4.4 m.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.