Eunji Song;Jeonghyu Yang;Youngmin Oh;Seungwook Hong;Dongjun Lee;Sangwan Lee;Hyunwoo Im;Taeho Shin;Jaeduk Han
{"title":"采用 40 纳米技术的 100-112-Gb/s 1.6 Vppd PAM-8 发射器与高摆幅 3 $+$ 1 混合 FFE 分路器","authors":"Eunji Song;Jeonghyu Yang;Youngmin Oh;Seungwook Hong;Dongjun Lee;Sangwan Lee;Hyunwoo Im;Taeho Shin;Jaeduk Han","doi":"10.1109/JSSC.2024.3492061","DOIUrl":null,"url":null,"abstract":"This article presents two eight-level pulse amplitude modulation (PAM-8) transmitters (TX) that achieve 100- and 112-Gb/s data rates, and a high output swing of 1.6 peak-to-peak differential voltage (Vppd) in 40-nm CMOS technology. The high-voltage driver is adopted to enhance the output swing level with the protective cascode and current-bleeding techniques. The hybrid <inline-formula> <tex-math>$3 {+} 1$ </tex-math></inline-formula> tap feed-forward equalizer (FFE) is implemented for efficient channel equalization. Two types of high-speed multiplexers are introduced for the final 4-to-1 serialization: a single-stack and single-stage multiplexer that achieves 33.3 Gbaud/s and a two-stage multiplexer at 37.3 Gbaud/s. Two prototype test chips are fabricated in 40-nm CMOS technology to evaluate the proposed multiplexer designs. The transmitters achieve the PAM-8 data rates of 100 Gb/s (for the single-stage multiplexer) and 112 Gb/s (for the two-stage multiplexer), with worst case eye-opening values of 45 and 57 mV. Their energy efficiencies are measured to be 3.35 and 4.56 pJ/bit.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 2","pages":"543-554"},"PeriodicalIF":5.6000,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"100–112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology\",\"authors\":\"Eunji Song;Jeonghyu Yang;Youngmin Oh;Seungwook Hong;Dongjun Lee;Sangwan Lee;Hyunwoo Im;Taeho Shin;Jaeduk Han\",\"doi\":\"10.1109/JSSC.2024.3492061\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents two eight-level pulse amplitude modulation (PAM-8) transmitters (TX) that achieve 100- and 112-Gb/s data rates, and a high output swing of 1.6 peak-to-peak differential voltage (Vppd) in 40-nm CMOS technology. The high-voltage driver is adopted to enhance the output swing level with the protective cascode and current-bleeding techniques. The hybrid <inline-formula> <tex-math>$3 {+} 1$ </tex-math></inline-formula> tap feed-forward equalizer (FFE) is implemented for efficient channel equalization. Two types of high-speed multiplexers are introduced for the final 4-to-1 serialization: a single-stack and single-stage multiplexer that achieves 33.3 Gbaud/s and a two-stage multiplexer at 37.3 Gbaud/s. Two prototype test chips are fabricated in 40-nm CMOS technology to evaluate the proposed multiplexer designs. The transmitters achieve the PAM-8 data rates of 100 Gb/s (for the single-stage multiplexer) and 112 Gb/s (for the two-stage multiplexer), with worst case eye-opening values of 45 and 57 mV. Their energy efficiencies are measured to be 3.35 and 4.56 pJ/bit.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"60 2\",\"pages\":\"543-554\"},\"PeriodicalIF\":5.6000,\"publicationDate\":\"2024-11-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10752934/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10752934/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
100–112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology
This article presents two eight-level pulse amplitude modulation (PAM-8) transmitters (TX) that achieve 100- and 112-Gb/s data rates, and a high output swing of 1.6 peak-to-peak differential voltage (Vppd) in 40-nm CMOS technology. The high-voltage driver is adopted to enhance the output swing level with the protective cascode and current-bleeding techniques. The hybrid $3 {+} 1$ tap feed-forward equalizer (FFE) is implemented for efficient channel equalization. Two types of high-speed multiplexers are introduced for the final 4-to-1 serialization: a single-stack and single-stage multiplexer that achieves 33.3 Gbaud/s and a two-stage multiplexer at 37.3 Gbaud/s. Two prototype test chips are fabricated in 40-nm CMOS technology to evaluate the proposed multiplexer designs. The transmitters achieve the PAM-8 data rates of 100 Gb/s (for the single-stage multiplexer) and 112 Gb/s (for the two-stage multiplexer), with worst case eye-opening values of 45 and 57 mV. Their energy efficiencies are measured to be 3.35 and 4.56 pJ/bit.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.