基于分布式脉冲特征提取和神经启发的 Boosted-SVM 分类器的模块化 DR 和 CMR 增强型抗伪影脑电图耳机

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-11-26 DOI:10.1109/JSSC.2024.3499914
Alireza Dabbaghian;Hossein Kassiri
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引用次数: 0

摘要

本文介绍了一种灵活的模块化脑电图(EEG)耳机的设计、开发和实验测试,用于长期癫痫监测和个性化治疗。采用系统和电路级技术来提高能源效率,同时确保高质量的脑电图记录和准确的癫痫发作检测。可穿戴原型包括用于高动态范围(DR)记录、运动伪影去除(MAR)和特征提取(FE)的数字有源电极(DAEs),以及用于患者特定分类、无线连接和共模抑制(CMR)增强的中央后端(BE)。DAEs通过分时数据总线进行通信,最大限度地减少了电线,实现了灵活的电极放置,最大限度地提高了系统的可扩展性。每个DAE通过以下方式提高记录质量:1)校准的CMR增强(>80-dB共模抑制比(CMRR)与1- $M\Omega $ ae - ae不匹配);2) SC陷波滤波对电力线噪声进行滤波;3)实时电极组织阻抗(ETI)测量,用于MAR和直流校正;4)具有17db DR增强的自动量程机构。In-AE FE将ae - be通信功率降低99.1%%, while pulse-based frequency sampling reduces FE power by 92.1%. A neuromorphic multiplier-less adaptively boosted support vector machine (SVM) maintains high detection accuracy with 97.6% less classification power than conventional designs. The chip was implemented in 180-nm CMOS, and the wearable system components (DAE, wireless, and CMR boards) were miniaturized. Experimental testing showed IIRN ( $0.64~\mu V_{\text {rms}}$ , 0.5–100 Hz), adjustable gain/bandwidth, DR (80 dB), SNDR (74.5 dB), and CMRR (89.2 dB without mismatch, >80 dB with mismatch). Measurement results also confirm the system’s effectiveness in motion artifact estimation and removal. In vivo measurements demonstrate the system’s efficacy and latency in detecting neurologically relevant events. Seizure detection results (96.4% sensitivity, 0.41 FPR, 1-s latency, zero SRAM usage) on prerecorded EEG data from 21 patients are also reported. The system is compared to state-of-the-art EEG recording and seizure detection systems, highlighting its advantages.
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Modular DR- and CMR-Boosted Artifact-Resilient EEG Headset With Distributed Pulse-Based Feature Extraction and Neuro-Inspired Boosted-SVM Classifier
This article presents the design, development, and experimental testing of a flexible, modular electroencephalography (EEG) headset for long-term epilepsy monitoring and individualized treatment. System- and circuit-level techniques are employed to improve energy efficiency while ensuring high-quality EEG recordings and accurate seizure detection. The wearable prototype includes digital active electrodes (DAEs) for high-dynamic-range (DR) recording, motion artifact removal (MAR), and feature extraction (FE), along with a central backend (BE) for patient-specific classification, wireless connectivity, and common-mode rejection (CMR) boosting. DAEs communicate through a time-shared data bus, minimizing wires and enabling flexible electrode placement, maximizing system scalability. Each DAE enhances recording quality with: 1) calibrated CMR boosting (>80-dB common-mode rejection ratio (CMRR) with 1- $M\Omega $ AE-to-AE mismatch); 2) SC notch filtering for power-line noise; 3) real-time electrode-tissue impedance (ETI) measurement for MAR and dc correction; and 4) an autoranging mechanism with 17-dB DR enhancement. In-AE FE cuts AE-to-BE communication power by 99.1%, while pulse-based frequency sampling reduces FE power by 92.1%. A neuromorphic multiplier-less adaptively boosted support vector machine (SVM) maintains high detection accuracy with 97.6% less classification power than conventional designs. The chip was implemented in 180-nm CMOS, and the wearable system components (DAE, wireless, and CMR boards) were miniaturized. Experimental testing showed IIRN ( $0.64~\mu V_{\text {rms}}$ , 0.5–100 Hz), adjustable gain/bandwidth, DR (80 dB), SNDR (74.5 dB), and CMRR (89.2 dB without mismatch, >80 dB with mismatch). Measurement results also confirm the system’s effectiveness in motion artifact estimation and removal. In vivo measurements demonstrate the system’s efficacy and latency in detecting neurologically relevant events. Seizure detection results (96.4% sensitivity, 0.41 FPR, 1-s latency, zero SRAM usage) on prerecorded EEG data from 21 patients are also reported. The system is compared to state-of-the-art EEG recording and seizure detection systems, highlighting its advantages.
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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