服务器cpu硬件记忆的案例

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-11-22 DOI:10.1109/LCA.2024.3505075
Farid Samandi;Natheesan Ratnasegar;Michael Ferdman
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引用次数: 0

摘要

服务器应用程序表现出高度的代码重复,因为它们处理许多类似的请求。反过来,重复执行相同的代码,通常使用相同的输入,突出了服务器软件执行的低效率,并建议将记忆作为提高性能的一种方法。记忆已经在软件中进行了广泛的探索,并且在文献中提出了几种硬件和硬件辅助的记忆方案。然而,这些工作针对的是数学或算法处理的记忆,而服务器应用程序则需要不同的方法。我们观察到,服务器中记忆的机会不是来自消除复杂计算的重复,而是来自消除软件编排代码的重复。这项工作研究了服务器中的硬件记忆,最终集中在一种模式上,即从间接跳转开始的指令序列。我们探讨了如何扩展乱序管道以支持这些指令序列的记忆,展示了服务器硬件记忆的潜力。使用26个应用程序(3个CloudSuite工作负载和23个vSwarm无服务器功能),我们展示了如何仅针对这一指令序列模式就可以记住这些服务器应用程序中超过10%(最多15.6%)的动态执行指令。
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A Case for Hardware Memoization in Server CPUs
Server applications exhibit a high degree of code repetition because they handle many similar requests. In turn, repeated execution of the same code, often with identical inputs, highlights an inefficiency in the execution of server software and suggests memoization as a way to improve performance. Memoization has been extensively explored in software, and several hardware- and hardware-assisted memoization schemes have been proposed in the literature. However, these works targeted memoization of mathematical or algorithmic processing, whereas server applications call for a different approach. We observe that the opportunity for memoization in servers arises not from eliminating the repetition of complex computation, but from eliminating the repetition of software orchestration code. This work studies hardware memoization in servers, ultimately focusing on one pattern, instruction sequences starting with indirect jumps. We explore how an out-of-order pipeline can be extended to support memoization of these instruction sequences, demonstrating the potential of hardware memoization for servers. Using 26 applications to make our case (3 CloudSuite workloads and 23 vSwarm serverless functions), we show how targeting just this one pattern of instruction sequences can memoize over 10% (up to 15.6%) of the dynamically executed instructions in these server applications.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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