Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adders

The stochastic time-to-digital converter (STDC) presents a novel approach to automating the design and implementation process, delivering high performance with strong resilience to process variations and layout-induced artifacts, although with increased silicon area and higher power consumption. To effectively lower these costs, this article presents a 10-bit fully synthesizable STDC design using a removal-free common-mode time dithering technique, which significantly reduces the numbers of delay cells and D-type flip-flops (DFFs) required for requisite levels of stochastic operation. This also reduces the size of the associated backend unary-to-binary (U2B) encoder. In addition, passive approximate adders are used to further reduce the area of the U2B for a compact design and significantly lower time for digital place and route. Two STDC prototypes are implemented in a 12-nm FinFET process with a conventional adder and passive approximate adder, respectively. STDC prototypes achieve energy efficiency of 160 dB, while the one using passive approximation adder improves the area efficiency from 28.6 to $19.1~{\mu \text {m}^{2}}$ /step.