A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering

This article reports a continuous-time (CT) pipelined delta-sigma ( $\Delta \Sigma $ ) analog-to-digital converter (ADC) featuring a proposed prefiltering scheme to tackle the DAC image issue. We introduce a fast-shunting route for high-speed DAC image current with a passive RC low-pass filter (LPF) on the quantization (QTZ) path. Together with another LPF on the signal path to align the delay, the CT front-end stage provides a residue signal with a small amplitude and smooth edges, relaxing the linearity requirements on the residue amplifier (RA) and the back-end stage. Specifically, the RC delay in the two LPFs is tracked over process variation, relaxing the signal leakage to the back end. For the back-end stage, we use an all-pass filter (APF) analog delay in a second-order CT cascade of integrators with feedforward (CIFF) $\Delta \Sigma $ modulator (DSM) with an input feedforward path. Such an APF can restore the unity signal transfer function (STF) under the influence of excess loop delay (ELD), thus simplifying the matching requirement between analog and digital domains’ transfer functions. Prototyped in a 28-nm CMOS process, the proposed ADC operates with a clock of 3.2GHz, occupying an active area of 0.104 mm2. It exhibits a 72-dB dynamic range (DR) and a 68.5-dB peak signal-to-noise-and-distortion ratio (SNDR) over a 160-MHz bandwidth (BW). The modulator consumes 36.2 mW, yielding 165-dB Schreier figure-of-merit (FOMs) based on the SNDR.