{"title":"采用新型自屏蔽负载开启Balun和宽带四阶LC梯形功率合闸的28纳米CMOS 90-180 GHz 15-18 dBm紧凑型功率放大器","authors":"Dawei Tang;Chun Yang;Peigen Zhou;Xiaoyue Xia;Zekun Li;Rui Zhang;Zhe Chen;Jixin Chen;Hao Gao;Wei Hong","doi":"10.1109/JSSC.2024.3518834","DOIUrl":null,"url":null,"abstract":"This article presents a compact four-way six-stage power amplifier (PA) operating in the 90–180 GHz range with 15–18 dBm saturated output power (<inline-formula> <tex-math>$P_{\\text {sat}}$ </tex-math></inline-formula>) in 28-nm bulk CMOS. A compact neutralized amplifier core utilizing a modified MOS capacitor is proposed, achieving a fourfold size reduction. The output network features a three-conductor self-shielding load-open (SSLO) balun-based dual LC-tank, and a slow wave coplanar waveguide (CPW) based 4th-order LC ladder, achieving a total loss of less than 2.5 dB. Staggered transformer-based broadband matching is employed to achieve a flat gain of 20 dB. At input, a parallel winding balun-based 1-to-8 power splitter is introduced to provide balanced power distribution. Measurements indicate that the PA achieves a maximum small-signal gain of 21 dB and delivers <inline-formula> <tex-math>$P_{\\text {sat}}$ </tex-math></inline-formula> more than 15 dBm, peaking at 18 dBm at 140 GHz. Compared to the state-of-the-art, this PA offers the widest operating band among F-band and D-band silicon-based PAs with comparable <inline-formula> <tex-math>$P_{\\text {sat}}$ </tex-math></inline-formula>, making it a promising candidate for high data rate and long-distance communication in D-/F-bands.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 8","pages":"2680-2693"},"PeriodicalIF":5.6000,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Compact 90–180 GHz, 15–18 dBm Power Amplifier With Novel Self-Shielding Load-Open Balun and Broadband Fourth-Order LC Ladder Power Combiner in 28-nm CMOS\",\"authors\":\"Dawei Tang;Chun Yang;Peigen Zhou;Xiaoyue Xia;Zekun Li;Rui Zhang;Zhe Chen;Jixin Chen;Hao Gao;Wei Hong\",\"doi\":\"10.1109/JSSC.2024.3518834\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents a compact four-way six-stage power amplifier (PA) operating in the 90–180 GHz range with 15–18 dBm saturated output power (<inline-formula> <tex-math>$P_{\\\\text {sat}}$ </tex-math></inline-formula>) in 28-nm bulk CMOS. A compact neutralized amplifier core utilizing a modified MOS capacitor is proposed, achieving a fourfold size reduction. The output network features a three-conductor self-shielding load-open (SSLO) balun-based dual LC-tank, and a slow wave coplanar waveguide (CPW) based 4th-order LC ladder, achieving a total loss of less than 2.5 dB. Staggered transformer-based broadband matching is employed to achieve a flat gain of 20 dB. At input, a parallel winding balun-based 1-to-8 power splitter is introduced to provide balanced power distribution. Measurements indicate that the PA achieves a maximum small-signal gain of 21 dB and delivers <inline-formula> <tex-math>$P_{\\\\text {sat}}$ </tex-math></inline-formula> more than 15 dBm, peaking at 18 dBm at 140 GHz. Compared to the state-of-the-art, this PA offers the widest operating band among F-band and D-band silicon-based PAs with comparable <inline-formula> <tex-math>$P_{\\\\text {sat}}$ </tex-math></inline-formula>, making it a promising candidate for high data rate and long-distance communication in D-/F-bands.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"60 8\",\"pages\":\"2680-2693\"},\"PeriodicalIF\":5.6000,\"publicationDate\":\"2024-12-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10816672/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10816672/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A Compact 90–180 GHz, 15–18 dBm Power Amplifier With Novel Self-Shielding Load-Open Balun and Broadband Fourth-Order LC Ladder Power Combiner in 28-nm CMOS
This article presents a compact four-way six-stage power amplifier (PA) operating in the 90–180 GHz range with 15–18 dBm saturated output power ($P_{\text {sat}}$ ) in 28-nm bulk CMOS. A compact neutralized amplifier core utilizing a modified MOS capacitor is proposed, achieving a fourfold size reduction. The output network features a three-conductor self-shielding load-open (SSLO) balun-based dual LC-tank, and a slow wave coplanar waveguide (CPW) based 4th-order LC ladder, achieving a total loss of less than 2.5 dB. Staggered transformer-based broadband matching is employed to achieve a flat gain of 20 dB. At input, a parallel winding balun-based 1-to-8 power splitter is introduced to provide balanced power distribution. Measurements indicate that the PA achieves a maximum small-signal gain of 21 dB and delivers $P_{\text {sat}}$ more than 15 dBm, peaking at 18 dBm at 140 GHz. Compared to the state-of-the-art, this PA offers the widest operating band among F-band and D-band silicon-based PAs with comparable $P_{\text {sat}}$ , making it a promising candidate for high data rate and long-distance communication in D-/F-bands.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.