A Multi-Core Series-Resonance CMOS Oscillator

Multi-core and series-resonance (SR) techniques have been proposed to achieve ultra-low phase noise (PN) performance. In this article, a scalable ring-coupling scheme is proposed for multi-core expansion. The mechanism provides intrinsic oscillation and PN reduction without compromising the passive network, specifically tailored for the SR oscillator. The dual closed ring paths in SR oscillators and the principle to establish core-to-core connections through cross-coupling are detailed. As a proof of concept, a ring-coupling quad-core and a hybrid-coupling hexa-core SR oscillator are implemented in a 65-nm complementary metal-oxide–semiconductor (CMOS) process. Normalized to 10 GHz, the quad-core design achieves a PN of −133.8 dBc/Hz with a figure of merit (FoM) of 188.3 dBc/Hz, while the hexa-core design achieves a PN of −137.7 dBc/Hz with an FoM of 187.1 dBc/Hz. To the best of our knowledge, this work reports the oscillator with the lowest PN using CMOS technology in open literature so far, albeit with tradeoffs in power and area.