{"title":"集成器件物理与电路动力学的pdae模型电力电子设备混合并行协同仿真框架","authors":"Qingyuan Shi;Chijie Zhuang;Jiapeng Liu;Bo Lin;Xiyu Peng;Dan Wu;Zhicheng Liu;Rong Zeng","doi":"10.1109/TPEL.2025.3534030","DOIUrl":null,"url":null,"abstract":"Optimizing high-performance power electronic equipment, such as power converters, requires multiscale simulations that incorporate the physics of power semiconductor devices and the dynamics of other circuit components, especially in conducting design of experiments (DoEs), defining the safe operating area of devices, and analyzing failures related to semiconductor devices. However, current methodologies either overlook the intricacies of device physics or do not achieve satisfactory computational speeds. To bridge this gap, this article proposes a hybrid-parallel collaborative (HPC) framework specifically designed to analyze the partial differential–algebraic equation (PDAE)-modeled power electronic equipment, integrating the device physics and circuit dynamics. The HPC framework employs a dynamic iteration to tackle the challenges inherent in solving the coupled nonlinear PDAE system and utilizes a hybrid-parallel computing strategy to reduce computing time. Physics-based system partitioning, along with hybrid-process-thread parallelization on shared and distributed memory, is employed, facilitating the simulation of hundreds of partial differential equations-modeled devices simultaneously without compromising speed. Experiments based on the hybrid-line commutated converter and reverse-blocking integrated gate-commutated thyristors are conducted under three typical real-world scenarios: semiconductor device optimization for the converter, converter design optimization, and device failure analysis. The HPC framework delivers simulation speed up to 60 times faster than the leading commercial software, while maintaining carrier-level accuracy in the experiments. This speedup becomes more pronounced as the number of semiconductor devices increases. This shows great potential for comprehensive analysis and collaborative optimization of devices and electronic power equipment, particularly in extreme conditions and failure scenarios.","PeriodicalId":13267,"journal":{"name":"IEEE Transactions on Power Electronics","volume":"40 6","pages":"8168-8178"},"PeriodicalIF":6.5000,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Hybrid-Parallel Collaborative Simulation Framework Integrating Device Physics With Circuit Dynamics for PDAE-Modeled Power Electronic Equipment\",\"authors\":\"Qingyuan Shi;Chijie Zhuang;Jiapeng Liu;Bo Lin;Xiyu Peng;Dan Wu;Zhicheng Liu;Rong Zeng\",\"doi\":\"10.1109/TPEL.2025.3534030\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Optimizing high-performance power electronic equipment, such as power converters, requires multiscale simulations that incorporate the physics of power semiconductor devices and the dynamics of other circuit components, especially in conducting design of experiments (DoEs), defining the safe operating area of devices, and analyzing failures related to semiconductor devices. However, current methodologies either overlook the intricacies of device physics or do not achieve satisfactory computational speeds. To bridge this gap, this article proposes a hybrid-parallel collaborative (HPC) framework specifically designed to analyze the partial differential–algebraic equation (PDAE)-modeled power electronic equipment, integrating the device physics and circuit dynamics. The HPC framework employs a dynamic iteration to tackle the challenges inherent in solving the coupled nonlinear PDAE system and utilizes a hybrid-parallel computing strategy to reduce computing time. Physics-based system partitioning, along with hybrid-process-thread parallelization on shared and distributed memory, is employed, facilitating the simulation of hundreds of partial differential equations-modeled devices simultaneously without compromising speed. Experiments based on the hybrid-line commutated converter and reverse-blocking integrated gate-commutated thyristors are conducted under three typical real-world scenarios: semiconductor device optimization for the converter, converter design optimization, and device failure analysis. The HPC framework delivers simulation speed up to 60 times faster than the leading commercial software, while maintaining carrier-level accuracy in the experiments. This speedup becomes more pronounced as the number of semiconductor devices increases. This shows great potential for comprehensive analysis and collaborative optimization of devices and electronic power equipment, particularly in extreme conditions and failure scenarios.\",\"PeriodicalId\":13267,\"journal\":{\"name\":\"IEEE Transactions on Power Electronics\",\"volume\":\"40 6\",\"pages\":\"8168-8178\"},\"PeriodicalIF\":6.5000,\"publicationDate\":\"2025-01-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Power Electronics\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10854913/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Power Electronics","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10854913/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Hybrid-Parallel Collaborative Simulation Framework Integrating Device Physics With Circuit Dynamics for PDAE-Modeled Power Electronic Equipment
Optimizing high-performance power electronic equipment, such as power converters, requires multiscale simulations that incorporate the physics of power semiconductor devices and the dynamics of other circuit components, especially in conducting design of experiments (DoEs), defining the safe operating area of devices, and analyzing failures related to semiconductor devices. However, current methodologies either overlook the intricacies of device physics or do not achieve satisfactory computational speeds. To bridge this gap, this article proposes a hybrid-parallel collaborative (HPC) framework specifically designed to analyze the partial differential–algebraic equation (PDAE)-modeled power electronic equipment, integrating the device physics and circuit dynamics. The HPC framework employs a dynamic iteration to tackle the challenges inherent in solving the coupled nonlinear PDAE system and utilizes a hybrid-parallel computing strategy to reduce computing time. Physics-based system partitioning, along with hybrid-process-thread parallelization on shared and distributed memory, is employed, facilitating the simulation of hundreds of partial differential equations-modeled devices simultaneously without compromising speed. Experiments based on the hybrid-line commutated converter and reverse-blocking integrated gate-commutated thyristors are conducted under three typical real-world scenarios: semiconductor device optimization for the converter, converter design optimization, and device failure analysis. The HPC framework delivers simulation speed up to 60 times faster than the leading commercial software, while maintaining carrier-level accuracy in the experiments. This speedup becomes more pronounced as the number of semiconductor devices increases. This shows great potential for comprehensive analysis and collaborative optimization of devices and electronic power equipment, particularly in extreme conditions and failure scenarios.
期刊介绍:
The IEEE Transactions on Power Electronics journal covers all issues of widespread or generic interest to engineers who work in the field of power electronics. The Journal editors will enforce standards and a review policy equivalent to the IEEE Transactions, and only papers of high technical quality will be accepted. Papers which treat new and novel device, circuit or system issues which are of generic interest to power electronics engineers are published. Papers which are not within the scope of this Journal will be forwarded to the appropriate IEEE Journal or Transactions editors. Examples of papers which would be more appropriately published in other Journals or Transactions include: 1) Papers describing semiconductor or electron device physics. These papers would be more appropriate for the IEEE Transactions on Electron Devices. 2) Papers describing applications in specific areas: e.g., industry, instrumentation, utility power systems, aerospace, industrial electronics, etc. These papers would be more appropriate for the Transactions of the Society which is concerned with these applications. 3) Papers describing magnetic materials and magnetic device physics. These papers would be more appropriate for the IEEE Transactions on Magnetics. 4) Papers on machine theory. These papers would be more appropriate for the IEEE Transactions on Power Systems. While original papers of significant technical content will comprise the major portion of the Journal, tutorial papers and papers of historical value are also reviewed for publication.