具有fir嵌入式正交混合相关和AoA定位的27.9 mw 802.15.4/4z 1T2R收发器

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2025-01-30 DOI:10.1109/JSSC.2025.3532896
Yunzhao Nie;Woogeun Rhee;Zhihua Wang
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引用次数: 0

摘要

本文提出了一种IEEE 802.15.4/4z超宽带(UWB)收发器架构,该架构采用有限脉冲响应(FIR)嵌入式正交混合相关(QHC)方法来实现低功耗和多径缓解。与rake接收器一样,所提出的模拟相关器用FIR抽头移位编码而不是UWB信号,从而降低了模拟相关中均衡器的设计复杂性。因此,每个FIR抽头的功耗降低了十倍以上。针对突发位置调制(BPM)信号的多径抑制问题,提出了一种基于最小二乘误差的FIR算法。为了验证所提出的fir嵌入式QHC方法,在65nm CMOS上实现了一个8ghz 1T2R收发器。收发器支持同步、BPM 0.98/7.8 Mbaud/s和精确定位。接收器达到−102 dbm灵敏度,消耗12.2 mW/信道,而FIR电路仅消耗5.3%。该芯片支持定位,平均到达时间(ToA)误差为1.5 cm,平均到达角(AoA)误差为3.8°。在占空比工作的情况下,收发器在有效载荷领域的功耗为27.9 mW,为0.98 Mbaud/s,是具有超宽带收发器的最低功耗。
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A 27.9-mW 802.15.4/4z 1T2R Transceiver With FIR-Embedded Quadrature Hybrid Correlation and AoA Localization
This article presents an IEEE 802.15.4/4z ultrawideband (UWB) transceiver architecture that employs a finite-impulse response (FIR)-embedded quadrature hybrid correlation (QHC) method for low power and multipath mitigation. Like a rake receiver, the proposed analog correlator shifts a code instead of a UWB signal with FIR taps to relax the design complexity of an equalizer in the analog correlation. As a result, the power consumption for each FIR tap is reduced by more than ten times. A least-square-error-based FIR algorithm is proposed for the multipath mitigation of a burst position modulation (BPM) signal. To validate the proposed FIR-embedded QHC method, an 8-GHz 1T2R transceiver is implemented in 65-nm CMOS. The transceiver supports synchronization, BPM at 0.98/7.8 Mbaud/s, and precise localization. The receiver achieves −102-dBm sensitivity and consumes 12.2 mW/channel, while the FIR circuits consume 5.3% only. The chip supports localization with an rms time-of-arrival (ToA) error of 1.5 cm and an rms angle-of-arrival (AoA) error of 3.8°. With the duty-cycled operation, the transceiver consumes 27.9 mW at 0.98 Mbaud/s in the payload field and features the lowest power consumption among HRP-capable UWB transceivers.
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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