协作内存重复数据删除与英特尔数据流加速器

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2025-01-09 DOI:10.1109/LCA.2025.3527458
Houxiang Ji;Minho Kim;Seonmu Oh;Daehoon Kim;Nam Sung Kim
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引用次数: 0

摘要

内存重复数据删除在减少超大规模服务器的内存消耗和总拥有成本(TCO)方面发挥着关键作用,特别是在大型语言模型的出现对内存资源提出了前所未有的需求时。但是,传统的基于cpu的内存重复数据删除会干扰协同运行的应用程序,严重影响对时间敏感的工作负载的性能。英特尔推出了片上数据流加速器(DSA),提供高性能的数据移动和转换功能,包括在重复数据删除中大量使用的比较和校验和计算。在这项工作中,我们通过选择性地将这些操作卸载到DSA,增强了广泛使用的内核空间内存重复数据删除功能——内核同页合并(ksm)。我们的评估表明,基于cpu的ksm可能导致共同运行应用程序的尾部延迟增加5.0 - 10.9倍,而基于dsa的ksm将延迟增加限制在1.6倍,同时实现了相当的内存节省。
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Cooperative Memory Deduplication With Intel Data Streaming Accelerator
Memory deduplication plays a critical role in reducing memory consumption and the total cost of ownership (TCO) in hyperscalers, particularly as the advent of large language models imposes unprecedented demands on memory resources. However, conventional CPU-based memory deduplication can interfere with co-running applications, significantly impacting the performance of time-sensitive workloads. Intel introduced the on-chip Data Streaming Accelerator (DSA), providing high-performance data movement and transformation capabilities, including comparison and checksum calculation, which are heavily utilized in the deduplication. In this work, we enhance a widely-used kernel-space memory deduplication feature, Kernel Samepage Merging (ksm), by selectively offloading these operations to the DSA. Our evaluation demonstrates that CPU-based ksm can lead to 5.0–10.9× increase in the tail latency of co-running applications while DSA-based ksm limits the latency increase to just 1.6× while achieving comparable memory savings.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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