同时双载波变压器耦合无源混频器优先接收器前端支持阻塞抑制

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2025-03-06 DOI:10.1109/JSSC.2025.3546082
Jamie C. Ye;Alain H. Antón;Sanaz Sadeghi;Russ H. Huang;Alyosha C. Molnar
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引用次数: 0

摘要

提出了一种高动态范围n径无源混频器优先接收机结构,该结构能够通过单个射频端口同时下变频两个任意频段。该架构由两个无源混频器组成,以串联配置,并带有变压器前端,以最大限度地减少混频器之间的交叉负载,同时仍然为两个频段提供阻抗透明性和相关的干扰抑制。在工作频率为2.8至4.3 GHz的16纳米FinFET工艺中进行的四相演示实现了6.8 - 9.7 db噪声系数(NF), 8.9 dbm带外(OOB)阻塞压缩(B1dB)和18.6 dbm带外(OOB)输入参考三阶截距点(IIP3),每通道功耗为25-28 mW。当其中一个混频器和相应的LO配置为针对阻塞器时,可实现14.4 dbm OOB-B1dB和27.6 dbm OOB-IIP3。本文详细介绍了初始原型的分析和设计,并提出了一个新的八阶段原型,使用相同的总体架构,但性能有所提高。新设计的工作频率为2.6至3.9 GHz,可实现4.0 - 7.6 db NF、12.5 dbm OOB-B1dB和22.1 dbm OOB-IIP3,每通道功耗为42-47 mW。
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A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression
A high dynamic range N-path passive mixer-first receiver architecture capable of simultaneously down-converting two arbitrary bands through a single RF port is presented. The architecture consists of two passive mixers arranged in a series configuration with a transformer front-end to minimize cross-loading between mixers while still providing impedance transparency and associated interference suppression for both bands. A four-phase demonstration in a 16-nm FinFET process operating from 2.8 to 4.3 GHz achieved 6.8–9.7-dB noise figure (NF), 8.9-dBm out-of-band (OOB) blocker compression (B1dB), and 18.6-dBm OOB input-referred third-order intercept point (IIP3) with 25–28 mW of power consumption per channel. When one of the mixers and the corresponding LO are configured to target a blocker, up to 14.4-dBm OOB-B1dB and 27.6-dBm OOB-IIP3 is achieved. This article elaborates on the analysis and design of the initial prototype and presents a new eight-phase prototype using the same general architecture but with improved performance. The new design operating from 2.6 to 3.9 GHz achieves 4.0–7.6-dB NF, 12.5-dBm OOB-B1dB, and 22.1-dBm OOB-IIP3 with 42–47 mW of power consumption per channel.
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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