Reducing Power and Cycle Requirement for FFT of ECG Signals through Low Level Arithmetic Optimizations for Cardiac Implantable Devices.

The Fast Fourier Transform or FFT remains to be the de facto standard in almost all disciplines for computing discrete Fourier transform. In embedded biomedical applications, efficient signal processing algorithms such as FFT for spectrum analysis are indispensable. The FFT is an O(Nlog₂N) algorithm which requires complex multiplication and addition using floating point numbers. On extremely power constrained embedded systems such as cardiac pacemakers, floating point operations are very cycle intensive and costly in terms of power. This work aims to exploit the repetitive nature of the Electrocardiogram (ECG) to reduce the number of total arithmetic operations required to execute a 128 point FFT routine. Using the simple concept of lookup tables, the proposed algorithm is able to improve both the performance and energy footprint for computing the FFT of the ECG data. An increase of 9.22% in computational speed and an improvement of 10.1% in battery life on a 32 bit embedded platform for a standard split-radix-2 FFT routine is achieved. The concept is tested using actual ECG data collected from PhysioNet.