XLA-NDP:用于近数据处理存储器上的深度学习模型训练的高效调度和代码生成

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-03-23 DOI:10.1109/LCA.2023.3261136
Jueon Park;Hyojin Sung
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引用次数: 0

摘要

深度学习(DL)模型训练必须解决内存瓶颈才能继续扩展。内存处理方法是一种可行的解决方案,因为它们将计算移到内存附近或内存中,从而减少了大量的数据移动。然而,要在这样的硬件上部署应用程序,端到端的软件支持对于有效的计算映射和调度以及可扩展的代码生成至关重要,但是没有考虑DL训练工作负载。在本文中,我们提出了XLA-NDP, NDPX的编译器和运行时解决方案,NDPX是一种与现有DL训练框架集成的近数据处理(NDP)架构。XLA-NDP卸载NDPX内核并调度它们与GPU内核重叠,以最大限度地提高基于GPU和NDPX成本的并行性,同时提供基于模板的代码生成器,并进行低级优化。实验表明,XLA-NDP在4个深度学习模型训练的GPU基线上提供了高达41%的加速(平均24%)。
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XLA-NDP: Efficient Scheduling and Code Generation for Deep Learning Model Training on Near-Data Processing Memory
Deep learning (DL) model training must address the memory bottleneck to continue scaling. Processing-in-memory approaches can be a viable solution as they move computations near or into the memory, reducing substantial data movement. However, to deploy applications on such hardware, end-to-end software support is crucial for efficient computation mapping and scheduling as well as extensible code generation, but no consideration has been made for DL training workloads. In this paper, we propose XLA-NDP, a compiler and runtime solution for NDPX, a near-data processing (NDP) architecture integrated with an existing DL training framework. XLA-NDP offloads NDPX kernels and schedules them to overlap with GPU kernels to maximize parallelism based on GPU and NDPX costs, while providing a template-based code generator with low-level optimizations. The experiments showed that XLA-NDP provides up to a 41% speedup (24% on average) over the GPU baseline for four DL model training.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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