{"title":"一种用于SDR应用的基于FPGA的可重构FIR滤波器","authors":"Lincoln Alexandre Paz Silva, F. A. Brito-Filho","doi":"10.4018/ijitn.326455","DOIUrl":null,"url":null,"abstract":"This article presents a proposal of a reconfigurable FIR filter capable of covering the most common wireless communication standards on software-defined radio applications. The filter was implemented using a low-cost field programmable gate array, Cyclone IV EP4CE22F17C6 model from Altera®. System design is presented together with simulation results. Validation is done for a 500 kHz base-band noisy signal. The synthesized design uses 5,259 logic elements of which 4,778 were used for combinational logic blocks and 513 for dedicated logic registers, which represents 22% of total used FPGA capacity. The maximum sampling frequency supported by the architecture is 23.24 MHz.","PeriodicalId":42285,"journal":{"name":"International Journal of Interdisciplinary Telecommunications and Networking","volume":null,"pages":null},"PeriodicalIF":0.4000,"publicationDate":"2023-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An FPGA-Based Reconfigurable FIR Filter for SDR Applications\",\"authors\":\"Lincoln Alexandre Paz Silva, F. A. Brito-Filho\",\"doi\":\"10.4018/ijitn.326455\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents a proposal of a reconfigurable FIR filter capable of covering the most common wireless communication standards on software-defined radio applications. The filter was implemented using a low-cost field programmable gate array, Cyclone IV EP4CE22F17C6 model from Altera®. System design is presented together with simulation results. Validation is done for a 500 kHz base-band noisy signal. The synthesized design uses 5,259 logic elements of which 4,778 were used for combinational logic blocks and 513 for dedicated logic registers, which represents 22% of total used FPGA capacity. The maximum sampling frequency supported by the architecture is 23.24 MHz.\",\"PeriodicalId\":42285,\"journal\":{\"name\":\"International Journal of Interdisciplinary Telecommunications and Networking\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.4000,\"publicationDate\":\"2023-07-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Interdisciplinary Telecommunications and Networking\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.4018/ijitn.326455\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"TELECOMMUNICATIONS\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Interdisciplinary Telecommunications and Networking","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4018/ijitn.326455","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"TELECOMMUNICATIONS","Score":null,"Total":0}
引用次数: 0
摘要
本文提出了一种可重构FIR滤波器的建议，该滤波器能够覆盖软件定义无线电应用中最常见的无线通信标准。过滤器采用Altera®的Cyclone IV EP4CE22F17C6型低成本现场可编程门阵列实现。给出了系统设计和仿真结果。对500kHz基带噪声信号进行了验证。综合设计使用5259个逻辑元件，其中4778个用于组合逻辑块，513个用于专用逻辑寄存器，占所用FPGA总容量的22%。该架构支持的最大采样频率为23.24MHz。
An FPGA-Based Reconfigurable FIR Filter for SDR Applications
This article presents a proposal of a reconfigurable FIR filter capable of covering the most common wireless communication standards on software-defined radio applications. The filter was implemented using a low-cost field programmable gate array, Cyclone IV EP4CE22F17C6 model from Altera®. System design is presented together with simulation results. Validation is done for a 500 kHz base-band noisy signal. The synthesized design uses 5,259 logic elements of which 4,778 were used for combinational logic blocks and 513 for dedicated logic registers, which represents 22% of total used FPGA capacity. The maximum sampling frequency supported by the architecture is 23.24 MHz.
期刊介绍：
The International Journal of Interdisciplinary Telecommunications and Networking (IJITN) examines timely and important telecommunications and networking issues, problems, and solutions from a multidimensional, interdisciplinary perspective for researchers and practitioners. IJITN emphasizes the cross-disciplinary viewpoints of electrical engineering, computer science, information technology, operations research, business administration, economics, sociology, and law. The journal publishes theoretical and empirical research findings, case studies, and surveys, as well as the opinions of leaders and experts in the field. The journal''s coverage of telecommunications and networking is broad, ranging from cutting edge research to practical implementations. Published articles must be from an interdisciplinary, rather than a narrow, discipline-specific viewpoint. The context may be industry-wide, organizational, individual user, or societal. Topics Covered: -Emerging telecommunications and networking technologies -Global telecommunications industry business modeling and analysis -Network management and security -New telecommunications applications, products, and services -Social and societal aspects of telecommunications and networking -Standards and standardization issues for telecommunications and networking -Strategic telecommunications management -Telecommunications and networking cultural issues and education -Telecommunications and networking hardware and software design -Telecommunications investments and new ventures -Telecommunications network modeling and design -Telecommunications regulation and policy issues -Telecommunications systems economics
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