重复UIS对先进汽车功率晶体管电学性能的影响

IF 0.5 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC Advances in Electrical and Electronic Engineering Pub Date : 2022-04-01 DOI:10.15598/aeee.v20i1.4120
J. Marek, J. Kozarik, M. Minárik, A. Chvála, L. Stuchlíková
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引用次数: 0

摘要

本文通过重复非箝位电感开关(UIS)测试研究了三种类型的汽车功率mosfet的退化,这种测试通常用于评估功率器件的雪崩鲁棒性。在开关应用中,电压尖峰可能出现大于计划电压的情况并不罕见,因此即使是最好的电子设计也可能遇到频繁的雪崩事件。因此,有必要分析重复雪崩对功率晶体管电性能的影响。本文重点介绍了主要电气参数的变换:导通电阻RON、击穿电压VBR、阈值电压VTH,以及相应的特性,以及电容。分析证明,DMOS晶体管不易受到重复雪崩的影响。受影响最大的参数是导通电阻RDSon,在6·10次应力脉冲后,RDSon增加了14%。参数的移位主要是由于阻塞PN结空间电荷区的热载流子注入,主要涉及栅极氧化物漏极区缺陷的生成/激活。对于TrenchMOS晶体管,观察到I - V曲线的显著变化,对RON产生了相当大的影响,其中观察到增加了22%。通过Synopsys Technology的计算机辅助设计(TCAD)仿真,验证了战壕角是主要退化区域。漏极电容CDG和输入电容Cin在三种分析结构中均有衰减。DLTS用于验证由应力引起的缺陷的生成/激活。在应力样品上检测到与SiO2和界面上的氧空位和杂质能级相对应的DLTS信号增加。
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The Influence of Repetitive UIS on Electrical Properties of Advanced Automotive Power Transistors
This paper investigates a degradation of three types of automotive power MOSFETs through repetitive Unclamped Inductive Switching (UIS) test typically used to evaluate the avalanche robustness of power devices. It is not uncommon in switching applications that greater than the planned voltage for voltage spikes can occur, so even the best electronic designs may encounter frequent avalanche events. Hence, there is a need to analyse the impact of repetitive avalanching on the electrical performance of power transistors. This article focused on the shift of main electrical parameters: on-resistance RON , breakdown voltage VBR, threshold voltage VTH , and corresponding characteristics, as well as capacitances. Analysis proved that DMOS transistors are less vulnerable to repetitive avalanching. The most impacted parameter was on-resistance RDSon, where a 14 % increase was observed after 6 · 10 stress pulses. The parameters shift is attributed to hot carrier injection in the space charge region of blocking PN junction and involves mainly defects generation/activation in the drain side region of the gate oxide. For the TrenchMOS transistor, a significant shift of I − V curves was observed with considerable impact on the RON where an increase of 22 % was observed. The trench corner is verified to be the mainly degraded region by Synopsys Technology Computer Aided Design (TCAD) simulations. Degradation of drain-gate capacitance CDG and input capacitance Cin was observed in all three types of analysed structures. DLTS was used to verify the generation/activation of defects invoked by stress. An increase of DLTS signal corresponding to energy levels of oxygen vacancies and impurities in SiO2 and on interfaces were detected on stressed samples.
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来源期刊
Advances in Electrical and Electronic Engineering
Advances in Electrical and Electronic Engineering ENGINEERING, ELECTRICAL & ELECTRONIC-
CiteScore
1.30
自引率
33.30%
发文量
30
审稿时长
25 weeks
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