自旋电子2M/7T内存计算单元

IF 1.6 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Journal of Low Power Electronics and Applications Pub Date : 2022-12-06 DOI:10.3390/jlpea12040063
A. Jafari, Christopher Münch, M. Tahoori
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引用次数: 0

摘要

在冯·诺伊曼架构上计算数据密集型应用导致显著的性能和能源开销。内存计算(CiM)的概念通过减少计算系统中的数据移动来解决冯·诺依曼机器的瓶颈。新兴的电阻式非易失性存储器技术以及易失性存储器(SRAM和DRAM)可用于实现基于CiM范例的架构。在本文中,我们提出了一种混合电池设计,通过结合磁隧道结(MTJ)和传统的6T-SRAM电池,为CiM提供了机会。该单元基于有状态的数组内计算执行CiM操作,与外围的无状态计算相比,具有更好的多操作数可扩展性。各种逻辑操作,如异或,或,IMP可以执行与所提出的设计。此外,所提出的单元还可以作为常规存储单元来读写易失性和非易失性数据。仿真结果表明,对于由连续位操作组成的数据库查询应用,所提出的CiM-A设计可以以最小的开销将延迟降低8倍,将能量降低13倍,从而提高常规内存体系结构的性能。
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A Spintronic 2M/7T Computation-in-Memory Cell
Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in the computing system. Emerging resistive non-volatile memory technologies, as well as volatile memories (SRAM and DRAM), can be used to realize architectures based on the CiM paradigm. In this paper, we propose a hybrid cell design to provide the opportunity for CiM by combining the magnetic tunnel junction (MTJ) and the conventional 6T-SRAM cell. The cell performs CiM operations based on stateful in-array computation, which has better scalability for multiple operands compared with stateless computation in the periphery. Various logic operations such as XOR, OR, and IMP can be performed with the proposed design. In addition, the proposed cell can also operate as a conventional memory cell to read and write volatile as well as non-volatile data. The obtained simulation results show that the proposed CiM-A design can increase the performance of regular memory architectures by reducing the delay by 8 times and the energy by 13 times for database query applications consisting of consecutive bitwise operations with minimum overhead.
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来源期刊
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications Engineering-Electrical and Electronic Engineering
CiteScore
3.60
自引率
14.30%
发文量
57
审稿时长
11 weeks
期刊最新文献
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