FAC-V:一种基于FPGA的RISC-V AES协处理器

IF 1.6 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Journal of Low Power Electronics and Applications Pub Date : 2022-09-27 DOI:10.3390/jlpea12040050
T. Gomes, P. Sousa, M. Silva, M. Ekpanyapong, S. Pinto
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引用次数: 0

摘要

在新的物联网(IoT)时代,嵌入式现场可编程门阵列(FPGA)技术能够部署定制的嵌入式物联网解决方案,以处理不同的应用要求和工作负载。FPGA技术与开放式RISC-V指令集架构(ISA)相结合,为创建具有不同加速器和协处理器的可重构物联网设备提供了无限的机会,这些加速器和协处理机与处理器紧密和松散耦合。在将物联网设备连接到互联网时,安全通信和数据交换是主要问题。然而,添加安全功能需要来自已经资源受限的物联网设备的额外功能。本文介绍了FAC-V协处理器,这是一种基于FPGA的RISC-V处理器解决方案,可以按照两种不同的耦合方式进行部署。FAC-V以很少的FPGA资源为代价,在硬件中实现了高级加密标准(AES),这是物联网低端设备中使用最广泛的加密算法之一。所进行的实验表明,与纯软件AES实现相比,FAC-V可以实现几个数量级的性能改进;例如,用AES-256加密16字节的消息可以达到8000×左右的性能增益,能耗为0.1μJ。
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FAC-V: An FPGA-Based AES Coprocessor for RISC-V
In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource-constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 μJ.
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来源期刊
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications Engineering-Electrical and Electronic Engineering
CiteScore
3.60
自引率
14.30%
发文量
57
审稿时长
11 weeks
期刊最新文献
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