用于加速内存密集型应用的计算CXL内存解决方案

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2022-12-05 DOI:10.1109/LCA.2022.3226482
Joonseop Sim;Soohong Ahn;Taeyoung Ahn;Seungyong Lee;Myunghyun Rhee;Jooyoung Kim;Kwangsik Shin;Donguk Moon;Euiseok Kim;Kyoung Park
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引用次数: 5

摘要

CXL接口是最新的技术,它通过在配置异构设备时提供内存共享协议来实现有效的内存扩展。然而,其有限的物理带宽可能成为新兴数据密集型应用程序的重要瓶颈。在这项工作中,我们提出了一种新的基于CXL的内存分解架构,并进行了现实世界的原型演示,该架构利用近数据处理克服了CXL接口的带宽限制。实验结果表明,与现有的CPU系统相比,我们的设计达到了1.9倍的性能/功耗效率。
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Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications
CXL interface is the up-to-date technology that enables effective memory expansion by providing a memory-sharing protocol in configuring heterogeneous devices. However, its limited physical bandwidth can be a significant bottleneck for emerging data-intensive applications. In this work, we propose a novel CXL-based memory disaggregation architecture with a real-world prototype demonstration, which overcomes the bandwidth limitation of the CXL interface using near-data processing. The experimental results demonstrate that our design achieves up to 1.9× better performance/power efficiency than the existing CPU system.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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