面向大密钥工作负载的高性能、高持久键值SSD设计

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-06-02 DOI:10.1109/LCA.2023.3282276

Chanyoung Park;Chun-Yi Liu;Kyungtae Kang;Mahmut Kandemir;Wonil Choi

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引用次数: 0

摘要

当前的KV-SSD设计假设了特定范围的典型工作负载，其中值的大小相当大，而键的大小相对较小。然而，我们发现(i)存在另一类工作负载，其密钥大小与其值大小相比相对较大;(ii)当前的KV-SSD设计在这种大密钥工作负载下存在长尾延迟和低存储利用率。为此，我们提出了一种新颖的KV-SSD(称为LK-SSD)设计，它可以减少尾部延迟，提高大密钥工作负载下的存储利用率，并对其进行增强，以延长设备寿命。通过大量的实验，我们证明LK-SSD更适合于大密钥工作负载的设计，也适用于典型的工作负载。

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Design of a High-Performance, High-Endurance Key-Value SSD for Large-Key Workloads

Current KV-SSD design assumes a specific range of typical workloads, where the size of values is quite large while that of keys is relatively small. However, we find that (i) there exist another spectrum of workloads, whose key sizes are relatively large, compared to their value sizes, and (ii) the current KV-SSD design suffers from long tail latencies and low storage utilization under such large-key workloads. To this end, we present novel design of a KV-SSD (called LK-SSD), which can reduce tail latences and increase storage utilization under large-key workloads, and add an enhancement to it for longer device lifetime. Through extensive experiments, we show that LK-SSD is more suitable design for the large-key workloads, and also available for the typical workloads.

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.