Comparative analysis between different approaches for single-phase PLLs

(cid:2) Abstract — This paper presents a comparative analysis between two distinct synchronizing circuits, which are usually applied as the core of control algorithms for single-phase power quality applications. One of these synchronizing circuits corresponds to a single-phase Phase-Locked Loop (PLL), implemented in α - β coordinates ( (cid:3)(cid:3) β -PLL), whereas the other one corresponds to the Enhanced PLL (E-PLL). The major contribution of this paper is to present a single-phase PLL oriented to power quality applications, with a very simple structure, capable to be synchronized with the fundamental component of an input signal (voltage or current), even considering substantial disturbances, such as, frequency deviations, phase shifts, harmonic components and amplitude variations. Simulation and experimental results, involving these two synchronizing circuits submitted to three different test cases, are provided in order to compare their transient and steady-state performance. Moreover, it is also presented a comparison involving the processing speed and memory requirements of these synchronizing circuits in the DSP TMS320F28335.