{"title":"比例-积分-导数控制锁相环的相位噪声分布研究","authors":"G. Konwar, T. Bezboruah","doi":"10.18178/ijeetc.10.5.369-376","DOIUrl":null,"url":null,"abstract":"Phase noise in a phase-locked loop is originated from reference oscillator, phase detector, loop filter, voltage controlled oscillator and frequency divider which make the system unstable by generating high phase noise at the output spectrum. In this work, a mathematical linear phase noise model is therefore developed to investigate the effect of reference noise, phase detector noise, voltage controlled oscillator noise, frequency divider noise and specifically the loop filter noise. For this purpose, the conventional active or passive low pass filter of the phase locked loop is replaced by a proportional-integral-derivative controller during acquisition. The noise problem of each component is formulated as a transfer function derived from linear analysis of the proposed mathematical noise model. The simulation results show that the effect of noise attenuation of voltage controlled oscillator is -40dB/decade while the noise attenuation of the reference noise, phase detector noise, proportional integral derivative controller noise and frequency divider noise are approximately -20dB/decade each. The 6.21GHz proposed proportional-integral-derivative controlled phase-locked loop is also highly stable with fast switching speed of 0.238nS at damping factor of 0.625 and phase margin of 92° for minimum phase noise.","PeriodicalId":37533,"journal":{"name":"International Journal of Electrical and Electronic Engineering and Telecommunications","volume":"1 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Studies on Phase Noise Profiles of Proportional-Integral-Derivative Controlled PLL\",\"authors\":\"G. Konwar, T. Bezboruah\",\"doi\":\"10.18178/ijeetc.10.5.369-376\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Phase noise in a phase-locked loop is originated from reference oscillator, phase detector, loop filter, voltage controlled oscillator and frequency divider which make the system unstable by generating high phase noise at the output spectrum. In this work, a mathematical linear phase noise model is therefore developed to investigate the effect of reference noise, phase detector noise, voltage controlled oscillator noise, frequency divider noise and specifically the loop filter noise. For this purpose, the conventional active or passive low pass filter of the phase locked loop is replaced by a proportional-integral-derivative controller during acquisition. The noise problem of each component is formulated as a transfer function derived from linear analysis of the proposed mathematical noise model. The simulation results show that the effect of noise attenuation of voltage controlled oscillator is -40dB/decade while the noise attenuation of the reference noise, phase detector noise, proportional integral derivative controller noise and frequency divider noise are approximately -20dB/decade each. The 6.21GHz proposed proportional-integral-derivative controlled phase-locked loop is also highly stable with fast switching speed of 0.238nS at damping factor of 0.625 and phase margin of 92° for minimum phase noise.\",\"PeriodicalId\":37533,\"journal\":{\"name\":\"International Journal of Electrical and Electronic Engineering and Telecommunications\",\"volume\":\"1 1\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Electrical and Electronic Engineering and Telecommunications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.18178/ijeetc.10.5.369-376\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"Computer Science\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Electrical and Electronic Engineering and Telecommunications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.18178/ijeetc.10.5.369-376","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"Computer Science","Score":null,"Total":0}
Studies on Phase Noise Profiles of Proportional-Integral-Derivative Controlled PLL
Phase noise in a phase-locked loop is originated from reference oscillator, phase detector, loop filter, voltage controlled oscillator and frequency divider which make the system unstable by generating high phase noise at the output spectrum. In this work, a mathematical linear phase noise model is therefore developed to investigate the effect of reference noise, phase detector noise, voltage controlled oscillator noise, frequency divider noise and specifically the loop filter noise. For this purpose, the conventional active or passive low pass filter of the phase locked loop is replaced by a proportional-integral-derivative controller during acquisition. The noise problem of each component is formulated as a transfer function derived from linear analysis of the proposed mathematical noise model. The simulation results show that the effect of noise attenuation of voltage controlled oscillator is -40dB/decade while the noise attenuation of the reference noise, phase detector noise, proportional integral derivative controller noise and frequency divider noise are approximately -20dB/decade each. The 6.21GHz proposed proportional-integral-derivative controlled phase-locked loop is also highly stable with fast switching speed of 0.238nS at damping factor of 0.625 and phase margin of 92° for minimum phase noise.
期刊介绍:
International Journal of Electrical and Electronic Engineering & Telecommunications. IJEETC is a scholarly peer-reviewed international scientific journal published quarterly, focusing on theories, systems, methods, algorithms and applications in electrical and electronic engineering & telecommunications. It provide a high profile, leading edge forum for academic researchers, industrial professionals, engineers, consultants, managers, educators and policy makers working in the field to contribute and disseminate innovative new work on Electrical and Electronic Engineering & Telecommunications. All papers will be blind reviewed and accepted papers will be published quarterly, which is available online (open access) and in printed version.