Memory-Efficient Probabilistic 2-D Finite Impulse Response (FIR) Filter

High memory/storage complexity poses severe challenges to achieving high throughput and high energy efficiency in discrete 2-D FIR filtering. This performance bottleneck is especially acute for embedded image or video applications, that use 2-D FIR processing extensively, because real-time processing and low power consumption are their paramount design objectives. Fortunately, most of such perception-based embedded applications possess so-called “inherent fault tolerance”, meaning slight computing accuracy degradation has a little negative effect on their quality of results, but has significant implication to their throughput, hardware implementation cost, and energy efficiency. This paper develops a novel stochastic-based 2-D FIR filtering architecture that exploits the well-known probabilistic convolution theorem to achieve both low hardware cost and high energy efficiency while achieving very high throughput and computing robustness. Our ASIC synthesis results show that stochastic-based architecture achieves L outputs per cycle with 97 and 81 percent less area-delay-product (ADP), and 77 and 67 percent less power consumption compared with the conventional structure and recently published state-of-the-art architecture, respectively, when the 2-D FIR filter size is 4 × 4, the input block size is L 1/4 4, and the image size is 512 × 512.