Logical Analysis for Switching Sequence Generation in 15-Level Reduced Switch MLI

Complexity in the implementation of the inverter circuit lies with the logic behind the generation of the switching pulse sequences using multicarrier-pulsewidth modulation (MC-PWM). The analysis of the switching sequence for the operation of 15 level multi-level inverter (MLI) topology using logical gates is introduced in this article. A 15-level reduced switch topology is proposed which consists of eight switches. The main focus is to analyze the procedure of generating a pulse pattern for the eight switches in the circuit and to obtain the logical expression. Key Findings: The input pulse for the generation of eight different pulse patterns is obtained by MC-PWM technique. Several MC-PWM techniques, including phase disposition (PD), alternate phase opposition disposition (APOD), and phase opposition disposition (POD), are available. POD were applied to the proposed reduced switch topology using the same logical expression and the results were analyzed. MATLAB/Simulink is employed in the execution of the simulation work. The desired pulse pattern is simulated in real time and generated with the assistance of dSPACE 1104. Various modulation index (MI) and several PWM algorithms are used to examine the total harmonic distortion (THD) comparison study.